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fix DT parsing of ports with implicit types

This commit is contained in:
Zachary Snow 2019-03-07 17:30:01 -05:00
parent 9ec9435cb0
commit f97e069ef0
1 changed files with 5 additions and 5 deletions
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10
src/Language/SystemVerilog/Parser/ParseDecl.hs
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@ -185,8 +185,6 @@ finalize (dir, typ, trips) =
-- internal; entrypoint of the critical portion of our parser
parseDTsAsComponents :: [DeclToken] -> [Component]
parseDTsAsComponents [] = []
parseDTsAsComponents [DTDir dir, DTIdent ident] =
[(dir, Implicit [], [(ident, [], Nothing)])]
parseDTsAsComponents l0 =
component : parseDTsAsComponents l4
where
@ -238,9 +236,11 @@ takeDir (DTDir dir : rest) = (dir , rest)
takeDir rest = (Local, rest)
takeType :: [DeclToken] -> ([Range] -> Type, [DeclToken])
takeType (DTType tf : rest) = (tf , rest)
takeType (DTIdent tn : rest) = (Alias tn, rest)
takeType rest = (Implicit, rest)
takeType (DTType tf : rest) = (tf , rest)
takeType (DTIdent tn : DTComma : rest) = (Implicit, DTIdent tn : DTComma : rest)
takeType (DTIdent tn : [ ]) = (Implicit, DTIdent tn : [ ])
takeType (DTIdent tn : rest) = (Alias tn, rest)
takeType rest = (Implicit, rest)
takeRanges :: [DeclToken] -> ([Range], [DeclToken])
takeRanges [] = ([], [])