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fix some silly edge cases in round-tripping output

This commit is contained in:
Zachary Snow 2019-02-22 13:55:48 -05:00
parent 546657d2c3
commit f895f4f045
2 changed files with 11 additions and 8 deletions
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17
Language/SystemVerilog/AST.hs
View File

@ -79,10 +79,10 @@ data Type
deriving Eq deriving Eq
instance Show Type where instance Show Type where
show (Reg r) = "reg " ++ (showRanges r) show (Reg r) = "reg" ++ (showRanges r)
show (Wire r) = "wire " ++ (showRanges r) show (Wire r) = "wire" ++ (showRanges r)
show (Logic r) = "logic " ++ (showRanges r) show (Logic r) = "logic" ++ (showRanges r)
show (Alias t r) = t ++ " " ++ (showRanges r) show (Alias t r) = t ++ (showRanges r)
data ModuleItem data ModuleItem
= Comment String = Comment String
@ -135,8 +135,8 @@ instance Show ModuleItem where
MIParameter nest -> show nest MIParameter nest -> show nest
MILocalparam nest -> show nest MILocalparam nest -> show nest
MIIntegerV nest -> show nest MIIntegerV nest -> show nest
PortDecl d r x -> printf "%s %s%s;" (show d) (showRanges r) x PortDecl d r x -> printf "%s%s %s;" (show d) (showRanges r) x
LocalNet t x v -> printf "%s%s%s;" (show t) x (showRangesOrAssignment v) LocalNet t x v -> printf "%s %s%s;" (show t) x (showRangesOrAssignment v)
AlwaysC k b -> printf "%s %s" (show k) (show b) AlwaysC k b -> printf "%s %s" (show k) (show b)
Assign a b -> printf "assign %s = %s;" (show a) (show b) Assign a b -> printf "assign %s = %s;" (show a) (show b)
Instance m params i ports Instance m params i ports
@ -173,8 +173,9 @@ showAssignment Nothing = ""
showAssignment (Just val) = " = " ++ show val showAssignment (Just val) = " = " ++ show val
showRanges :: [Range] -> String showRanges :: [Range] -> String
showRanges = concat . (map rangeToString) showRanges [] = ""
where rangeToString d = (showRange $ Just d) ++ "\b" showRanges l = " " ++ (concat $ map rangeToString l)
where rangeToString d = init $ showRange $ Just d
showRange :: Maybe Range -> String showRange :: Maybe Range -> String
showRange Nothing = "" showRange Nothing = ""

2
Language/SystemVerilog/Parser/Parse.y
View File

@ -219,6 +219,7 @@ PortDeclsFollow :: { [ModuleItem] }
PortDecl(delim) :: { [ModuleItem] } PortDecl(delim) :: { [ModuleItem] }
: "inout" opt(NetType) Dimensions Identifiers delim { portDeclToModuleItems Inout $2 $3 (zip $4 (repeat Nothing)) } : "inout" opt(NetType) Dimensions Identifiers delim { portDeclToModuleItems Inout $2 $3 (zip $4 (repeat Nothing)) }
| "input" opt(NetType) Dimensions Identifiers delim { portDeclToModuleItems Input $2 $3 (zip $4 (repeat Nothing)) } | "input" opt(NetType) Dimensions Identifiers delim { portDeclToModuleItems Input $2 $3 (zip $4 (repeat Nothing)) }
| "output" Dimensions Identifiers delim { portDeclToModuleItems Output Nothing $2 (zip $3 (repeat Nothing)) }
| "output" "wire" Dimensions Identifiers delim { portDeclToModuleItems Output (Just Wire ) $3 (zip $4 (repeat Nothing)) } | "output" "wire" Dimensions Identifiers delim { portDeclToModuleItems Output (Just Wire ) $3 (zip $4 (repeat Nothing)) }
| "output" "reg" Dimensions VariablePortIdentifiers delim { portDeclToModuleItems Output (Just Reg ) $3 $4 } | "output" "reg" Dimensions VariablePortIdentifiers delim { portDeclToModuleItems Output (Just Reg ) $3 $4 }
| "output" "logic" Dimensions VariablePortIdentifiers delim { portDeclToModuleItems Output (Just Logic) $3 $4 } | "output" "logic" Dimensions VariablePortIdentifiers delim { portDeclToModuleItems Output (Just Logic) $3 $4 }
@ -300,6 +301,7 @@ RangeOrType :: { Either Range () }
EventControl :: { Sense } EventControl :: { Sense }
: "@" "(" Sense ")" { $3 } : "@" "(" Sense ")" { $3 }
| "@" "(" "*" ")" { SenseStar } | "@" "(" "*" ")" { SenseStar }
| "@" "(*)" { SenseStar }
| "@" "*" { SenseStar } | "@" "*" { SenseStar }
| "@*" { SenseStar } | "@*" { SenseStar }