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fix ordering of and outputs

This commit is contained in:
Zachary Snow 2020-09-13 23:24:21 -04:00
parent a170536382
commit eb908b8db7
1 changed files with 1 additions and 1 deletions
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2
src/Language/SystemVerilog/Parser/Parse.y
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@ -781,7 +781,7 @@ NOutputGate :: { (Expr, Identifier, [LHS], Expr) }
: DelayControlOrNil opt(Identifier) "(" NOutputGateItems { ($1, fromMaybe "" $2, fst $4, snd $4) }
NOutputGateItems :: { ([LHS], Expr) }
: Expr ")" { ([], $1) }
| Expr "," NOutputGateItems { (fst $3 ++ [toLHS $1], snd $3) }
| Expr "," NOutputGateItems { (toLHS $1 : fst $3, snd $3) }
DelayControlOrNil :: { Expr }
: DelayControl { $1 }
| {- empty -} { Nil }