some cleanup throughout the SystemVerilog module

src/Language/SystemVerilog/AST/Stmt.hs

@@ -12,8 +12,7 @@ module Language.SystemVerilog.AST.Stmt
     , CaseKW (..)
     , Case
     , ActionBlock  (..)
-    , PropertyExpr (..)
-    , PESPBinOp    (..)
+    , PropExpr     (..)
     , SeqMatchItem
     , SeqExpr      (..)
     , AssertionItem
@@ -144,24 +143,21 @@ instance Show ActionBlock where
     show (ActionBlockElse Nothing   s ) = printf " else %s" (show s)
     show (ActionBlockElse (Just s1) s2) = printf " %s else %s" (show s1) (show s2)
 
-data PropertyExpr
-    = PESE SeqExpr
-    | PESPBinOp SeqExpr PESPBinOp PropertyExpr
+data PropExpr
+    = PropExpr SeqExpr
+    | PropExprImpliesO  SeqExpr PropExpr
+    | PropExprImpliesNO SeqExpr PropExpr
+    | PropExprFollowsO  SeqExpr PropExpr
+    | PropExprFollowsNO SeqExpr PropExpr
+    | PropExprIff PropExpr PropExpr
     deriving Eq
-instance Show PropertyExpr where
-    show (PESE se) = show se
-    show (PESPBinOp a o b) = printf "(%s %s %s)" (show a) (show o) (show b)
-data PESPBinOp
-    = ImpliesO
-    | ImpliesNO
-    | FollowedByO
-    | FollowedByNO
-    deriving (Eq, Ord)
-instance Show PESPBinOp where
-    show ImpliesO     = "|->"
-    show ImpliesNO    = "|=>"
-    show FollowedByO  = "#-#"
-    show FollowedByNO = "#=#"
+instance Show PropExpr where
+    show (PropExpr se) = show se
+    show (PropExprImpliesO  a b) = printf "(%s |-> %s)" (show a) (show b)
+    show (PropExprImpliesNO a b) = printf "(%s |=> %s)" (show a) (show b)
+    show (PropExprFollowsO  a b) = printf "(%s #-# %s)" (show a) (show b)
+    show (PropExprFollowsNO a b) = printf "(%s #=# %s)" (show a) (show b)
+    show (PropExprIff a b) = printf "(%s and %s)" (show a) (show b)
 type SeqMatchItem = Either (LHS, AsgnOp, Expr) (Identifier, Args)
 data SeqExpr
     = SeqExpr Expr
@@ -195,7 +191,7 @@ instance Show Assertion where
         printf "assert property (%s)%s" (show p) (show a)
 
 data PropertySpec
-    = PropertySpec (Maybe Sense) (Maybe Expr) PropertyExpr
+    = PropertySpec (Maybe Sense) (Maybe Expr) PropExpr
     deriving Eq
 instance Show PropertySpec where
     show (PropertySpec ms me pe) =

src/Language/SystemVerilog/Parser/Lex.x

@@ -14,17 +14,19 @@
  - Trying to thread the IO Monad through alex's interface would be very
  - convoluted. The operations performed are not effectful, and are type safe.
  -}
+
 {-# OPTIONS_GHC -fno-warn-unused-imports #-}
 -- The above pragma gets rid of annoying warning caused by alex 3.2.4. This has
 -- been fixed on their development branch, so this can be removed once they roll
 -- a new release. (no new release as of 3/29/2018)
+
 module Language.SystemVerilog.Parser.Lex (lexFile) where
 
 import System.FilePath (dropFileName)
 import System.Directory (findFile)
 import System.IO.Unsafe (unsafePerformIO)
 import qualified Data.Map.Strict as Map
-import Data.List (span, elemIndex, isPrefixOf, dropWhileEnd)
+import Data.List (span, elemIndex, dropWhileEnd)
 import Data.Maybe (isJust, fromJust)
 
 import Language.SystemVerilog.Parser.Tokens

src/Language/SystemVerilog/Parser/Parse.y

@@ -1,3 +1,11 @@
+{- sv2v
+ - Author: Zachary Snow <zach@zachjs.com>
+ - Original Parser Author: Tom Hawkins <tomahawkins@gmail.com>
+ -
+ - This file has been *heavily* modified and extended from the original version
+ - in tomahawkins/verilog. I have added support for numerous SystemVerilog
+ - constructs, which has necessitated rewriting nearly all of this.
+ -}
 {
 module Language.SystemVerilog.Parser.Parse (descriptions) where
 
@@ -204,7 +212,6 @@ string             { Token Lit_string      _ _ }
 "<<<="             { Token Sym_lt_lt_lt_eq _ _ }
 ">>>="             { Token Sym_gt_gt_gt_eq _ _ }
 
-directive          { Token Spe_Directive _ _ }
 
 -- operator precedences, from *lowest* to *highest*
 %nonassoc NoElse
@@ -233,7 +240,6 @@ directive          { Token Spe_Directive _ _ }
 %right REDUCE_OP "!" "~" "++" "--"
 %left  "(" ")" "[" "]" "." "'"
 
-
 %%
 
 opt(p) :: { Maybe a }
@@ -249,15 +255,12 @@ Description :: { Description }
   : Part(ModuleKW   , "endmodule"   ) { $1 }
   | Part(InterfaceKW, "endinterface") { $1 }
   | PackageItem { PackageItem $1 }
-  | Directive   { Directive $1 }
-
-Directive :: { String }
-  : directive { tokenString $1 }
 
 Type :: { Type }
-  : PartialType         Dimensions { $1 Unspecified $2 }
-  | PartialType Signing Dimensions { $1 $2 $3 }
+  : TypeNonIdent { $1 }
   | Identifier Dimensions { Alias $1 $2 }
+TypeNonIdent :: { Type }
+  : PartialType OptSigning Dimensions { $1 $2 $3 }
 PartialType :: { Signing -> [Range] -> Type }
   : NetType                                 { \Unspecified ->        Net           $1    }
   | IntegerVectorType                       {                        IntegerVector $1    }
@@ -265,10 +268,6 @@ PartialType :: { Signing -> [Range] -> Type }
   | NonIntegerType                          { \Unspecified -> \[] -> NonInteger    $1    }
   | "enum"   opt(Type) "{" EnumItems   "}"  { \Unspecified -> Enum   $2 $4 }
   | "struct" Packing   "{" StructItems "}"  { \Unspecified -> Struct $2 $4 }
-TypeNonIdent :: { Type }
-  : PartialType         Dimensions { $1 Unspecified $2 }
-  | PartialType Signing Dimensions { $1 $2 $3 }
-
 CastingType :: { Type }
   : IntegerVectorType { IntegerVector $1 Unspecified [] }
   | IntegerAtomType   { IntegerAtom   $1 Unspecified    }
@@ -278,6 +277,9 @@ CastingType :: { Type }
 Signing :: { Signing }
   : "signed"   { Signed   }
   | "unsigned" { Unsigned }
+OptSigning :: { Signing }
+  : Signing { $1 }
+  | {- empty -} { Unspecified }
 
 NetType :: { NetType }
   : "supply0"   { TSupply0   }
@@ -318,8 +320,7 @@ StructItem :: { [(Type, Identifier)] }
   : Type Identifiers ";" { map (\a -> ($1, a)) $2 }
 
 Packing :: { Packing }
-  : "packed" Signing { Packed $2 }
-  | "packed"         { Packed Unspecified }
+  : "packed" OptSigning { Packed $2 }
   | {- empty -}         { Unpacked }
 
 Part(begin, end) :: { Description }
@@ -464,20 +465,17 @@ SimpleImmediateAssertionStatement :: { Assertion }
   -- TODO: Add support for assume and cover
 
 PropertySpec :: { PropertySpec }
-  : opt(ClockingEvent) "disable" "iff" "(" Expr ")" PropertyExpr { PropertySpec $1 (Just $5) $7 }
-  | opt(ClockingEvent)                              PropertyExpr { PropertySpec $1 (Nothing) $2 }
+  : opt(ClockingEvent) "disable" "iff" "(" Expr ")" PropExpr { PropertySpec $1 (Just $5) $7 }
+  | opt(ClockingEvent)                              PropExpr { PropertySpec $1 (Nothing) $2 }
 
--- TODO: This is pretty incomplete!
-PropertyExpr :: { PropertyExpr }
-  : SeqExpr          { PESE $1 }
-  | SeqExpr PESPBinOp PropertyExpr { PESPBinOp $1 $2 $3 }
-  -- | "(" PropertyExpr ")"  { [] }
-
-PESPBinOp :: { PESPBinOp }
-  : "|->" { ImpliesO     }
-  | "|=>" { ImpliesNO    }
-  | "#-#" { FollowedByO  }
-  | "#=#" { FollowedByNO }
+PropExpr :: { PropExpr }
+  : SeqExpr { PropExpr $1 }
+  | SeqExpr "|->" PropExpr { PropExprImpliesO  $1 $3 }
+  | SeqExpr "|=>" PropExpr { PropExprImpliesNO $1 $3 }
+  | SeqExpr "#-#" PropExpr { PropExprFollowsO  $1 $3 }
+  | SeqExpr "#=#" PropExpr { PropExprFollowsNO $1 $3 }
+  | PropExpr "iff" PropExpr { PropExprIff $1 $3 }
+  -- | "(" PropExpr ")"  { $2 }
 
 SeqExpr :: { SeqExpr }
   : Expr { SeqExpr $1 }
@@ -572,8 +570,7 @@ TFItems :: { [Decl] }
   |                     ";" { [] }
 
 ParamType :: { Type }
-  : PartialType         Dimensions { $1 Unspecified $2 }
-  | PartialType Signing Dimensions { $1 $2 $3 }
+  : PartialType OptSigning Dimensions { $1 $2 $3 }
   | DimensionsNonEmpty { Implicit Unspecified $1 }
   | Signing Dimensions { Implicit $1          $2 }
 
@@ -853,7 +850,6 @@ GenItem :: { GenItem }
   | GenBlock                                             { uncurry GenBlock $1 }
   | "case" "(" Expr ")" GenCases opt(GenCaseDefault) "endcase" { GenCase $3 $5 $6 }
   | "for" "(" Identifier "=" Expr ";" Expr ";" GenvarIteration ")" GenBlock { (uncurry $ GenFor ($3, $5) $7 $9) $11  }
-  -- TODO: We should restrict it to the module items that are actually allowed.
   | ModuleItem { genItemsToGenItem $ map GenModuleItem $1 }
 
 GenBlock :: { (Maybe Identifier, [GenItem]) }

src/Language/SystemVerilog/Parser/Tokens.hs

@@ -1,3 +1,10 @@
+{- sv2v
+ - Author: Tom Hawkins <tomahawkins@gmail.com>
+ - Modified by: Zachary Snow <zach@zachjs.com>
+ -
+ - This file is largely the same as when we forked from tomahawkins/verilog. Of
+ - course, some additional token names have been added.
+ -}
 module Language.SystemVerilog.Parser.Tokens
     ( Token     (..)
     , TokenName (..)
@@ -10,12 +17,16 @@ import Text.Printf
 tokenString :: Token -> String
 tokenString (Token _ s _) = s
 
-data Position = Position String Int Int deriving Eq
+data Position
+    = Position String Int Int
+    deriving Eq
 
 instance Show Position where
     show (Position f l c) = printf "%s:%d:%d" f l c
 
-data Token = Token TokenName String Position deriving (Show, Eq)
+data Token
+    = Token TokenName String Position
+    deriving (Show, Eq)
 
 data TokenName
     = KW_alias
@@ -338,6 +349,5 @@ data TokenName
     | Sym_amp_amp_amp
     | Sym_lt_lt_lt_eq
     | Sym_gt_gt_gt_eq
-  | Spe_Directive
     | Unknown
     deriving (Show, Eq)