luke/sv2v
1
0
Fork 0
mirror of https://github.com/zachjs/sv2v.git synced 2026-09-03 08:33:46 +02:00
Code Issues Packages Projects Releases Wiki Activity

omit reference file for verilog-compatible test inputs

Browse Source
This commit is contained in:
Zachary Snow
2020-12-08 11:39:17 -07:00
parent 2081f6a32a
commit e72d372d73
19 changed files with 8 additions and 32 deletions
Download Patch File Download Diff File Expand all files Collapse all files
test/basic/attr.v
-1
View File
@@ -1 +0,0 @@
`include "attr.sv"
test/basic/div.v
-1
View File
@@ -1 +0,0 @@
`include "div.sv"
test/basic/else_prec.v
-2
View File
@@ -1,2 +0,0 @@
// Reference file is already plain Verilog
`include "else_prec.sv"
test/basic/flatten.v
-2
View File
@@ -1,2 +0,0 @@
// iverilog supports multi-dimensional packed arrays
`include "flatten.sv"
test/basic/flatten_three.v
-2
View File
@@ -1,2 +0,0 @@
// iverilog supports multi-dimensional packed arrays
`include "flatten_three.sv"
test/basic/gate.v
-2
View File
@@ -1,2 +0,0 @@
// This test is for parser coverge only.
`include "gate.sv"
test/basic/packed_array_shadow.v
-2
View File
@@ -1,2 +0,0 @@
// iverilog has support for packed arrays and functions
`include "packed_array_shadow.sv"
test/basic/shift.v
-1
View File
@@ -1 +0,0 @@
`include "shift.sv"
test/basic/stmt_task.v
-1
View File
@@ -1 +0,0 @@
`include "stmt_task.sv"
test/basic/typeof_op.v
-1
View File
@@ -1 +0,0 @@
`include "typeof_op.sv"