minor fixes

src/Language/SystemVerilog/Parser/Parse.y

@@ -890,7 +890,6 @@ parseError a = case a of
   Token t s p : _ -> error $ "Parse error: unexpected token '" ++ s ++ "' (" ++ show t ++ ") at " ++ show p ++ "."
 
 genItemsToGenItem :: [GenItem] -> GenItem
-genItemsToGenItem [] = error "genItemsToGenItem given empty list!"
 genItemsToGenItem [x] = x
 genItemsToGenItem xs = GenBlock Nothing xs
 

src/Language/SystemVerilog/Parser/ParseDecl.hs

@@ -223,6 +223,7 @@ parseDTsAsDeclsAndAsgns tokens =
 isAsgnToken :: DeclToken -> Bool
 isAsgnToken (DTBit             _) = True
 isAsgnToken (DTConcat          _) = True
+isAsgnToken (DTDot             _) = True
 isAsgnToken (DTAsgnNBlk      _ _) = True
 isAsgnToken (DTAsgn (AsgnOp _) _) = True
 isAsgnToken _ = False