minor multi-packed verbosity improvement

src/Convert/MultiplePacked.hs

@@ -93,8 +93,8 @@ combineRanges r1 r2 = r
         combine (s1, e1) (s2, e2) =
             (simplify upper, simplify lower)
             where
-                size1 = rangeSize (s1, e1)
-                size2 = rangeSize (s2, e2)
+                size1 = rangeSizeHiLo (s1, e1)
+                size2 = rangeSizeHiLo (s2, e2)
                 lower = BinOp Add e2 (BinOp Mul e1 size2)
                 upper = BinOp Add (BinOp Mul size1 size2)
                             (BinOp Sub lower (Number "1"))

src/Language/SystemVerilog/AST/Expr.hs

@@ -19,6 +19,7 @@ module Language.SystemVerilog.AST.Expr
     , showExprOrRange
     , simplify
     , rangeSize
+    , rangeSizeHiLo
     , endianCondExpr
     , endianCondRange
     , dimensionsSize
@@ -274,8 +275,12 @@ rangeSize :: Range -> Expr
 rangeSize (s, e) =
     endianCondExpr (s, e) a b
     where
-        a = simplify $ BinOp Add (BinOp Sub s e) (Number "1")
-        b = simplify $ BinOp Add (BinOp Sub e s) (Number "1")
+        a = rangeSizeHiLo (s, e)
+        b = rangeSizeHiLo (e, s)
+
+rangeSizeHiLo :: Range -> Expr
+rangeSizeHiLo (hi, lo) =
+    simplify $ BinOp Add (BinOp Sub hi lo) (Number "1")
 
 -- chooses one or the other expression based on the endianness of the given
 -- range; [hi:lo] chooses the first expression