obey declaration order in reference output

The latest verion of iverilog enforces declaration ordering more
strictly. Update a few test cases to match. sv2v still supports
out-of-order items on a best-effort basis.

test/core/multipack.v

@@ -1,12 +1,5 @@
 module Example;
 
-    initial
-        $monitor("%b %b %b %b %b %b %b %b %b",
-            arr1, arr2, arr3,
-            arr4, arr5, arr6,
-            arr7, arr8, arr9
-        );
-
     reg [14:0] arr1;
     reg [14:0] arr2;
     reg [14:0] arr3;
@@ -43,4 +36,11 @@ module Example;
         #1; arr9[(4-1)*3+:3] = arr9[(4-2)*3+:3];
     end
 
+    initial
+        $monitor("%b %b %b %b %b %b %b %b %b",
+            arr1, arr2, arr3,
+            arr4, arr5, arr6,
+            arr7, arr8, arr9
+        );
+
 endmodule

test/core/package_order.v

@@ -1,9 +1,8 @@
-module evil_mdl (
+module evil_mdl (foo);
-    output reg [evil_pkg_B-1:0] foo
-);
     localparam evil_pkg_Z = 1;
     localparam evil_pkg_A = evil_pkg_Z;
     localparam evil_pkg_B = evil_pkg_Z;
+    output reg [evil_pkg_B-1:0] foo;
     initial foo = evil_pkg_A;
 endmodule
 

test/core/reorder.v

@@ -9,8 +9,8 @@ module top;
             assign brr[0] = 1;
             initial $display("%b", brr);
             if (YES) begin : blk2
-                assign crr[0] = 1;
                 wire [19:0] crr;
+                assign crr[0] = 1;
                 initial $display("%b", crr);
             end
         end