mirror of https://github.com/zachjs/sv2v.git
added partial support for implicitly sized arrays
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454afa97a3
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@ -592,6 +592,7 @@ DeclOrStmtTokens(delim) :: { [DeclToken] }
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| "<=" opt(DelayOrEventControl) Expr delim { [DTAsgnNBlk $2 $3] }
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| "<=" opt(DelayOrEventControl) Expr delim { [DTAsgnNBlk $2 $3] }
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DeclOrStmtToken :: { DeclToken }
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DeclOrStmtToken :: { DeclToken }
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: "," { DTComma }
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: "," { DTComma }
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| "[" "]" { DTAutoDim }
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| PartSelect { DTRange $1 }
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| PartSelect { DTRange $1 }
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| Identifier { DTIdent $1 }
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| Identifier { DTIdent $1 }
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| Direction { DTDir $1 }
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| Direction { DTDir $1 }
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@ -46,6 +46,7 @@ import Language.SystemVerilog.AST
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-- [PUBLIC]: combined (irregular) tokens for declarations
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-- [PUBLIC]: combined (irregular) tokens for declarations
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data DeclToken
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data DeclToken
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= DTComma
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= DTComma
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| DTAutoDim
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| DTAsgn AsgnOp Expr
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| DTAsgn AsgnOp Expr
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| DTAsgnNBlk (Maybe Timing) Expr
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| DTAsgnNBlk (Maybe Timing) Expr
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| DTRange (PartSelectMode, Range)
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| DTRange (PartSelectMode, Range)
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@ -384,10 +385,22 @@ takeRanges (token : tokens) =
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case token of
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case token of
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DTRange (NonIndexed, r) -> (r : rs, rest )
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DTRange (NonIndexed, r) -> (r : rs, rest )
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DTBit s -> (asRange s : rs, rest )
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DTBit s -> (asRange s : rs, rest )
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DTAutoDim ->
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case rest of
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(DTAsgn AsgnOpEq (Pattern l) : _) -> autoDim l
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(DTAsgn AsgnOpEq (Concat l) : _) -> autoDim l
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_ -> ([] , token : tokens)
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_ -> ([] , token : tokens)
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_ -> ([] , token : tokens)
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where
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where
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(rs, rest) = takeRanges tokens
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(rs, rest) = takeRanges tokens
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asRange s = (Number "0", BinOp Sub s (Number "1"))
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asRange s = (Number "0", BinOp Sub s (Number "1"))
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autoDim :: [a] -> ([Range], [DeclToken])
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autoDim l =
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((lo, hi) : rs, rest)
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where
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n = length l
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lo = Number "0"
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hi = Number $ show (n - 1)
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-- Matching DTAsgnNBlk here allows tripLookahead to work both for standard
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-- Matching DTAsgnNBlk here allows tripLookahead to work both for standard
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-- declarations and in `parseDTsAsDeclOrAsgn`, where we're checking for an
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-- declarations and in `parseDTsAsDeclOrAsgn`, where we're checking for an
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@ -6,8 +6,7 @@ module top;
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logic [3:0] data;
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logic [3:0] data;
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} packet_t;
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} packet_t;
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initial begin
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initial begin
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// TODO: Add support for implicitly sized arrays.
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logic [1:0] array[] = '{ 2'b10, 2'b01, 2'b11, 2'b00 };
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logic [1:0] array[4] = '{ 2'b10, 2'b01, 2'b11, 2'b00 };
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packet_t packet = {<<4{ {<<2{array}} }};
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packet_t packet = {<<4{ {<<2{array}} }};
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$display("packet addr = %b", packet.addr);
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$display("packet addr = %b", packet.addr);
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$display("packet data = %b", packet.data);
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$display("packet data = %b", packet.data);
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