logic conversion supports generate block scoping

test/basic/logic_tf.sv

@@ -13,4 +13,31 @@ module top;
         $display("%b %b %b %b", x, y, z, f());
         $display("%b %b %b %b", x, y, z, f());
     end
+
+    generate
+        begin : A
+            logic x;
+            begin : B
+                logic x;
+            end
+            begin : C
+                logic x;
+            end
+            assign x = B.x ^ C.x;
+        end
+    endgenerate
+    initial A.B.x = 0;
+    assign A.C.x = 1;
+    initial $display("%b %b %b %b", x, A.x, A.B.x, A.C.x);
+
+    logic t2l;
+    task t2;
+        input logic t2l;
+        top.t2l = t2l;
+    endtask
+    initial begin
+        $display("%b", t2l);
+        t2(1);
+        $display("%b", t2l);
+    end
 endmodule

test/basic/logic_tf.v

@@ -17,4 +17,31 @@ module top;
         $display("%b %b %b %b", x, y, z, f(0));
         $display("%b %b %b %b", x, y, z, f(0));
     end
+
+    generate
+        begin : A
+            wire x;
+            begin : B
+                reg x;
+            end
+            begin : C
+                wire x;
+            end
+            assign x = B.x ^ C.x;
+        end
+    endgenerate
+    initial A.B.x = 0;
+    assign A.C.x = 1;
+    initial $display("%b %b %b %b", x, A.x, A.B.x, A.C.x);
+
+    reg t2l;
+    task t2;
+        input reg t2l;
+        top.t2l = t2l;
+    endtask
+    initial begin
+        $display("%b", t2l);
+        t2(1);
+        $display("%b", t2l);
+    end
 endmodule