remove extraneous explicit unsigned (resolves #45)

src/Convert.hs

@@ -40,6 +40,7 @@ import qualified Convert.Struct
 import qualified Convert.Typedef
 import qualified Convert.UnbasedUnsized
 import qualified Convert.Unique
+import qualified Convert.Unsigned
 
 type Phase = [AST] -> [AST]
 
@@ -68,6 +69,7 @@ phases excludes =
     , Convert.Typedef.convert
     , Convert.UnbasedUnsized.convert
     , Convert.Unique.convert
+    , Convert.Unsigned.convert
     , Convert.Package.convert
     , Convert.Enum.convert
     , Convert.NestPI.convert

src/Convert/Unsigned.hs

@@ -0,0 +1,26 @@
+{- sv2v
+ - Author: Zachary Snow <zach@zachjs.com>
+ -
+ - Conversion for `unsigned` types.
+ -
+ - Verilog-2005 makes `reg`, `wire`, etc. unsigned by default. Further, it does
+ - not have the `unsigned` keyword. This conversion ensures we either mark a
+ - data type as `signed` or leave the signing unspecified.
+ -}
+
+module Convert.Unsigned (convert) where
+
+import Convert.Traverse
+import Language.SystemVerilog.AST
+
+convert :: [AST] -> [AST]
+convert =
+    map $
+    traverseDescriptions $
+    traverseModuleItems $
+    traverseTypes convertType
+
+convertType :: Type -> Type
+convertType (IntegerVector t Unsigned rs) = IntegerVector t Unspecified rs
+convertType (Net           t Unsigned rs) = Net           t Unspecified rs
+convertType other = other

sv2v.cabal

@@ -86,6 +86,7 @@ executable sv2v
     Convert.Traverse
     Convert.UnbasedUnsized
     Convert.Unique
+    Convert.Unsigned
     -- sv2v CLI modules
     Job
   ghc-options:

test/basic/unsigned.sv

@@ -0,0 +1,7 @@
+module top;
+    logic [3:0] arr;
+    always_comb
+        for (int unsigned i = 0; i < 4; i++)
+            arr[i] = i;
+    initial $display(arr);
+endmodule

test/basic/unsigned.v

@@ -0,0 +1,9 @@
+module top;
+    reg [3:0] arr;
+    always @* begin : block_name
+        integer i;
+        for (i = 0; i < 4; i++)
+            arr[i] = i;
+    end
+    initial $display(arr);
+endmodule

test/lib/functions.sh

@@ -56,12 +56,16 @@ assertConverts() {
     assertTrue "conversion of $ac_file not stable after the second iteration" $?
     # using sed to remove quoted strings
     filtered=`sed -E 's/"([^"]|\")+"//g' "$ac_tmpa"`
-    echo "$filtered" | grep "\$bits" > /dev/null
+    # check for various things iverilog accepts which we don't want to output
-    assertFalse "conversion of $ac_file still contains \$bits" $?
+    PATTERNS="\$bits\|\$dimensions\|\$unpacked_dimensions\|\$left\|\$right\|\$low\|\$high\|\$increment\|\$size"
+    echo "$filtered" | grep "$PATTERNS" > /dev/null
+    assertFalse "conversion of $ac_file still contains dimension queries" $?
     echo "$filtered" | grep "\]\[" > /dev/null
     assertFalse "conversion of $ac_file still contains multi-dim arrays" $?
     echo "$filtered" | egrep "\s(int\|bit\|logic\|byte\|struct\|enum\|longint\|shortint)\s"
     assertFalse "conversion of $ac_file still contains SV types" $?
+    echo "$filtered" | grep "[^$]unsigned" > /dev/null
+    assertFalse "conversion of $ac_file still contains unsigned keyword" $?
 }
 
 # convert SystemVerilog source file(s)