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fix multiple instantiations on one line

This commit is contained in:
Zachary Snow 2019-03-08 17:01:49 -05:00
parent b5b9fdb37e
commit bddb8ceaff
1 changed files with 8 additions and 5 deletions
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13
src/Language/SystemVerilog/Parser/ParseDecl.hs
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@ -124,7 +124,7 @@ parseDTsAsModuleItems tokens =
-- internal; parser for module instantiations
parseDTsAsIntantiations :: [DeclToken] -> [ModuleItem]
parseDTsAsIntantiations (DTIdent name : tokens) =
if not (all isInstance rest)
if not (all isInstanceOrComma rest)
then error $ "instantiations mixed with other items: " ++ (show rest)
else map (uncurry $ Instance name params) instances
where
@ -132,10 +132,13 @@ parseDTsAsIntantiations (DTIdent name : tokens) =
case head tokens of
DTParams ps -> (ps, tail tokens)
_ -> ([], tokens)
instances = map (\(DTInstance inst) -> inst) rest
isInstance :: DeclToken -> Bool
isInstance (DTInstance _) = True
isInstance _ = False
instances =
map (\(DTInstance inst) -> inst) $
filter (DTComma /=) $ rest
isInstanceOrComma :: DeclToken -> Bool
isInstanceOrComma (DTInstance _) = True
isInstanceOrComma DTComma = True
isInstanceOrComma _ = False
parseDTsAsIntantiations tokens =
error $
"DeclTokens contain instantiations, but start with non-ident: "