mirror of
https://github.com/zachjs/sv2v.git
synced 2026-09-02 02:17:13 +02:00
limited progress on typeof signedness
- ensure concats and repeats stay unsigned - defer unbased-unsized conversion to enable cast semantics - disable inaccurate folding of binary operations of based numbers - fix typeof and size cast binop signedness logic - fix typeof $unsigned and $signed - test harness allows production of `integer unsigned`
This commit is contained in:
Zachary Snow
@@ -34,6 +34,9 @@ module top;
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$display("args %b", $size(RamPair, 1'dx));
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`EXHAUST(Ram);
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`EXHAUST(Ram[0]);
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`EXHAUST($unsigned(Ram[0]));
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`EXHAUST($signed(Ram[0]));
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`EXHAUST(Ram[0+:2]);
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`EXHAUST(Ram[1+:2]);
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`EXHAUST(Ram[0][2-:1]);
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@@ -23,6 +23,36 @@ module top;
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$display(1);
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$display(160);
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$display(16, 16, 1'bx);
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$display(16, 16, 1'bx);
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$display(1, 1, 1'bx);
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$display(16, 16, 1'bx);
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$display(1, 1, 1'bx);
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$display(1, 1, 1'bx);
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$display(1);
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$display(0);
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$display(16);
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$display(16, 16, 1'bx);
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$display(15, 15, 1'bx);
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$display(0, 0, 1'bx);
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$display(15, 15, 1'bx);
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$display(0, 0, 1'bx);
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$display(1, 1, 1'bx);
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$display(1);
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$display(0);
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$display(16);
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$display(16, 16, 1'bx);
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$display(15, 15, 1'bx);
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$display(0, 0, 1'bx);
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$display(15, 15, 1'bx);
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$display(0, 0, 1'bx);
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$display(1, 1, 1'bx);
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$display(1);
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$display(0);
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$display(16);
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$display(2, 2, 16);
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$display(0, 0, 16);
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$display(1, 1, 1);
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@@ -0,0 +1,195 @@
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`define ASSERT_SIGNEDNESS(expr, signedness_str, signedness_val) \
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initial begin \
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type(expr) typeof; \
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logic signed [$bits(expr):0] ones; \
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logic [$bits(expr):0] extd; \
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typeof = 1'sb1; \
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ones = 1'sb1; \
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extd = typeof; \
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if (signedness_val != (extd == ones)) \
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$display(`"FAIL: expected (expr) to be treated as signedness_str extd=%b`", extd); \
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end
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`define ASSERT_SIGNED(expr) `ASSERT_SIGNEDNESS(expr, signed, 1)
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`define ASSERT_UNSIGNED(expr) `ASSERT_SIGNEDNESS(expr, unsigned, 0)
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`define MAKE_PRIM(typ) \
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typ typ``_unspecified = 1; \
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typ unsigned typ``_unsigned = 1; \
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typ signed typ``_signed = 1; \
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`ASSERT_SIGNED(typ``_signed) \
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`ASSERT_UNSIGNED(typ``_unsigned)
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`define MAKE_PRIM_SIGNED(typ) \
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`MAKE_PRIM(typ) \
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`ASSERT_SIGNED(typ``_unspecified)
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`define MAKE_PRIM_UNSIGNED(typ) \
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`MAKE_PRIM(typ) \
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`ASSERT_UNSIGNED(typ``_unspecified)
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module top;
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logic signed x;
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logic signed [1:0] y;
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assign x = 0;
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assign y = 2;
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type(x % y) z;
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assign z = x % y;
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logic [3:0] w;
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assign w = z;
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initial #1 $display("%b %b %b %b", x, y, z, w);
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`MAKE_PRIM_SIGNED(byte)
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`MAKE_PRIM_SIGNED(shortint)
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`MAKE_PRIM_SIGNED(int)
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`MAKE_PRIM_SIGNED(integer)
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`MAKE_PRIM_SIGNED(longint)
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`MAKE_PRIM_UNSIGNED(bit)
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`MAKE_PRIM_UNSIGNED(reg)
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`MAKE_PRIM_UNSIGNED(logic)
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reg signed [5:0] arr;
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`ASSERT_SIGNED(0)
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`ASSERT_SIGNED('sb0)
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`ASSERT_UNSIGNED('b0)
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`ASSERT_UNSIGNED('o0)
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`ASSERT_UNSIGNED('d0)
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`ASSERT_UNSIGNED('h0)
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`ASSERT_SIGNED('sb0)
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`ASSERT_SIGNED('so0)
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`ASSERT_SIGNED('sd0)
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`ASSERT_SIGNED('sh0)
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`ASSERT_UNSIGNED({1'b0})
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`ASSERT_UNSIGNED({1'o0})
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`ASSERT_UNSIGNED({1'd0})
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`ASSERT_UNSIGNED({1'h0})
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`ASSERT_UNSIGNED({1'sb0})
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`ASSERT_UNSIGNED({1'so0})
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`ASSERT_UNSIGNED({1'sd0})
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`ASSERT_UNSIGNED({1'sh0})
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`ASSERT_UNSIGNED({reg_unspecified})
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`ASSERT_UNSIGNED({reg_unsigned})
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`ASSERT_UNSIGNED({reg_signed})
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`ASSERT_UNSIGNED({1 {1'b0}})
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`ASSERT_UNSIGNED({1 {1'o0}})
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`ASSERT_UNSIGNED({1 {1'd0}})
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`ASSERT_UNSIGNED({1 {1'h0}})
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`ASSERT_UNSIGNED({1 {1'sb0}})
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`ASSERT_UNSIGNED({1 {1'so0}})
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`ASSERT_UNSIGNED({1 {1'sd0}})
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`ASSERT_UNSIGNED({1 {1'sh0}})
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`ASSERT_UNSIGNED({1 {reg_unspecified}})
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`ASSERT_UNSIGNED({1 {reg_unsigned}})
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`ASSERT_UNSIGNED({1 {reg_signed}})
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`ASSERT_SIGNED($signed(reg_unspecified))
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`ASSERT_SIGNED($signed(reg_unsigned))
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`ASSERT_SIGNED($signed(reg_signed))
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`ASSERT_UNSIGNED($unsigned(reg_unspecified))
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`ASSERT_UNSIGNED($unsigned(reg_unsigned))
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`ASSERT_UNSIGNED($unsigned(reg_signed))
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`define UNIOP_ALWAYS_UNSIGNED(op) \
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`ASSERT_UNSIGNED(op 2'sb11) \
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`ASSERT_UNSIGNED(op 2'b11) \
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`ASSERT_UNSIGNED(op reg_signed) \
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`ASSERT_UNSIGNED(op reg_unsigned)
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`define UNIOP_SAME_SIGN(op) \
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`ASSERT_SIGNED(op 2'sb11) \
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`ASSERT_UNSIGNED(op 2'b11) \
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`ASSERT_SIGNED(op reg_signed) \
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`ASSERT_UNSIGNED(op reg_unsigned)
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`UNIOP_ALWAYS_UNSIGNED(!)
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`UNIOP_SAME_SIGN(~)
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`UNIOP_SAME_SIGN(+)
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`UNIOP_SAME_SIGN(-)
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`UNIOP_ALWAYS_UNSIGNED(&)
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`UNIOP_ALWAYS_UNSIGNED(~&)
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`UNIOP_ALWAYS_UNSIGNED(|)
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`UNIOP_ALWAYS_UNSIGNED(~|)
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`UNIOP_ALWAYS_UNSIGNED(^)
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`UNIOP_ALWAYS_UNSIGNED(~^)
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`define BINOP_BOTH_SIGNED(op) \
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`ASSERT_SIGNED(reg_signed op reg_signed) \
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`ASSERT_UNSIGNED(reg_unsigned op reg_signed) \
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`ASSERT_UNSIGNED(reg_signed op reg_unsigned) \
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`ASSERT_UNSIGNED(reg_unsigned op reg_unsigned) \
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`ASSERT_UNSIGNED(reg_unsigned op arr) \
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`ASSERT_UNSIGNED(arr op reg_unsigned) \
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`ASSERT_SIGNED(arr op arr) \
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`ASSERT_SIGNED(arr op reg_signed) \
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`ASSERT_SIGNED(reg_signed op arr) \
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`ASSERT_SIGNED(1'sb1 op 2'sb11) \
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`ASSERT_UNSIGNED(1'b1 op 2'sb11) \
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`ASSERT_UNSIGNED(1'sb1 op 2'b11) \
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`ASSERT_UNSIGNED(1'b1 op 2'b11)
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`define BINOP_FIRST_SIGNED(op) \
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`ASSERT_SIGNED(reg_signed op reg_signed) \
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`ASSERT_UNSIGNED(reg_unsigned op reg_signed) \
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`ASSERT_SIGNED(reg_signed op reg_unsigned) \
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`ASSERT_UNSIGNED(reg_unsigned op reg_unsigned) \
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`ASSERT_SIGNED(1'sb1 op 2'sb11) \
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`ASSERT_UNSIGNED(1'b1 op 2'sb11) \
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`ASSERT_SIGNED(1'sb1 op 2'b11) \
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`ASSERT_UNSIGNED(1'b1 op 2'b11)
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`define BINOP_NEVER_SIGNED(op) \
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`ASSERT_UNSIGNED(reg_signed op reg_signed) \
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`ASSERT_UNSIGNED(reg_unsigned op reg_signed) \
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`ASSERT_UNSIGNED(reg_signed op reg_unsigned) \
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`ASSERT_UNSIGNED(reg_unsigned op reg_unsigned) \
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`ASSERT_UNSIGNED(1'sb1 op 2'sb11) \
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`ASSERT_UNSIGNED(1'b1 op 2'sb11) \
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`ASSERT_UNSIGNED(1'sb1 op 2'b11) \
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`ASSERT_UNSIGNED(1'b1 op 2'b11)
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`BINOP_NEVER_SIGNED(&& )
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`BINOP_NEVER_SIGNED(|| )
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`BINOP_NEVER_SIGNED(-> )
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`BINOP_NEVER_SIGNED(<->)
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`BINOP_BOTH_SIGNED( & )
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`BINOP_BOTH_SIGNED( ^ )
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`BINOP_BOTH_SIGNED( ~^ )
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`BINOP_BOTH_SIGNED( | )
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`BINOP_BOTH_SIGNED( * )
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`BINOP_BOTH_SIGNED( / )
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`BINOP_BOTH_SIGNED( + )
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`BINOP_BOTH_SIGNED( - )
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`BINOP_FIRST_SIGNED(** )
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`BINOP_FIRST_SIGNED(<< )
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`BINOP_FIRST_SIGNED(>> )
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`BINOP_FIRST_SIGNED(<<<)
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`BINOP_FIRST_SIGNED(>>>)
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`BINOP_NEVER_SIGNED(== )
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`BINOP_NEVER_SIGNED(!= )
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`BINOP_NEVER_SIGNED(===)
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`BINOP_NEVER_SIGNED(!==)
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`BINOP_NEVER_SIGNED(==?)
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`BINOP_NEVER_SIGNED(!=?)
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`BINOP_NEVER_SIGNED(< )
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`BINOP_NEVER_SIGNED(<= )
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`BINOP_NEVER_SIGNED(> )
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`BINOP_NEVER_SIGNED(>= )
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`ASSERT_UNSIGNED(4'('0))
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`ASSERT_UNSIGNED(3'('x))
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`ASSERT_SIGNED(2'(1'sb1))
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`ASSERT_SIGNED(10'(2'sb11))
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`ASSERT_UNSIGNED(10'(2'b11))
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`ASSERT_UNSIGNED(2'(1'b1))
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`ASSERT_SIGNED(2'(reg_signed))
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`ASSERT_UNSIGNED(2'(reg_unsigned))
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`ASSERT_SIGNED(arr)
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`ASSERT_UNSIGNED(arr[0])
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`ASSERT_UNSIGNED(arr[5:0])
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`ASSERT_UNSIGNED(arr[1+:2])
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`ASSERT_UNSIGNED(arr[1-:2])
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endmodule
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@@ -0,0 +1,30 @@
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`define MAKE_PRIM(typ, base, size) \
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base [size-1:0] typ``_unspecified = 1; \
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base unsigned [size-1:0] typ``_unsigned = 1; \
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base signed [size-1:0] typ``_signed = 1;
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module top;
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wire signed x;
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wire signed [1:0] y;
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assign x = 0;
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assign y = 2;
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wire signed [1:0] z;
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assign z = x % y;
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wire [3:0] w;
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assign w = z;
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initial #1 $display("%b %b %b %b", x, y, z, w);
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`MAKE_PRIM(byte, reg, 8)
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`MAKE_PRIM(shortint, reg, 16)
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`MAKE_PRIM(int, reg, 32)
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integer integer_unspecified = 1;
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integer unsigned integer_unsigned = 1;
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integer signed integer_signed = 1;
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`MAKE_PRIM(longint, reg, 64)
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`MAKE_PRIM(bit, wire, 1)
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`MAKE_PRIM(reg, reg, 1)
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`MAKE_PRIM(logic, wire, 1)
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reg signed [5:0] arr;
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endmodule
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