support simple bundle interfaces

- fix position modport-to-modport bindings
- inout logics converted to regs become outputs
This commit is contained in:
Zachary Snow
2020-06-03 20:26:17 -04:00
parent 589261a91b
commit b6f4f690e7
5 changed files with 165 additions and 35 deletions
+43
View File
@@ -0,0 +1,43 @@
interface bundle;
logic [1:0] index;
logic clock;
logic [3:0] inp;
logic out;
endinterface
module rotator(bundle b);
initial b.index = 0;
always @(posedge b.clock)
b.index <= b.index + 1;
endmodule
module setter(bundle b);
initial b.inp = '1;
always @(posedge b.clock)
b.inp[b.index] <= b.out;
endmodule
module reducer(bundle b);
assign b.out = ^b.inp;
endmodule
module clocker(bundle b);
initial begin
b.clock <= 0;
forever
#5 b.clock <= ~b.clock;
end
endmodule
module top;
bundle b();
rotator rot(b);
setter set(b);
reducer red(b);
clocker clk(b);
initial begin
$monitor("%b %b %b %b", b.index, b.clock, b.inp, b.out);
#100;
$finish;
end
endmodule