support simple bundle interfaces

- fix position modport-to-modport bindings
- inout logics converted to regs become outputs

test/basic/interface_bundle.sv

@@ -0,0 +1,43 @@
+interface bundle;
+    logic [1:0] index;
+    logic clock;
+    logic [3:0] inp;
+    logic out;
+endinterface
+
+module rotator(bundle b);
+    initial b.index = 0;
+    always @(posedge b.clock)
+        b.index <= b.index + 1;
+endmodule
+
+module setter(bundle b);
+    initial b.inp = '1;
+    always @(posedge b.clock)
+        b.inp[b.index] <= b.out;
+endmodule
+
+module reducer(bundle b);
+    assign b.out = ^b.inp;
+endmodule
+
+module clocker(bundle b);
+    initial begin
+        b.clock <= 0;
+        forever
+            #5 b.clock <= ~b.clock;
+    end
+endmodule
+
+module top;
+    bundle b();
+    rotator rot(b);
+    setter set(b);
+    reducer red(b);
+    clocker clk(b);
+    initial begin
+        $monitor("%b %b %b %b", b.index, b.clock, b.inp, b.out);
+        #100;
+        $finish;
+    end
+endmodule

test/basic/interface_bundle.v

@@ -0,0 +1,38 @@
+module impl(b_index, b_clock, b_inp, b_out);
+    output reg [1:0] b_index;
+    output reg b_clock;
+    output reg [3:0] b_inp;
+    output wire b_out;
+
+    initial b_index = 0;
+    always @(posedge b_clock)
+        b_index <= b_index + 1;
+
+    initial b_inp = 4'b1111;
+    always @(posedge b_clock)
+        b_inp[b_index] <= b_out;
+
+    assign b_out = ^b_inp;
+
+    initial begin
+        b_clock <= 0;
+        forever
+            #5 b_clock <= ~b_clock;
+    end
+endmodule
+
+module top;
+    wire [1:0] b_index;
+    wire b_clock;
+    wire [3:0] b_inp;
+    wire b_out;
+
+    impl impl(b_index, b_clock, b_inp, b_out);
+
+    initial begin
+        $monitor("%b %b %b %b", b_index, b_clock, b_inp, b_out);
+        #100;
+        $finish;
+    end
+endmodule
+