hacky support for 'part-select addressing'

src/Language/SystemVerilog/Parser/Parse.y

@@ -591,6 +591,9 @@ DeclAsgn :: { (Identifier, Expr) }
 
 Range :: { Range }
   : "[" Expr ":"  Expr "]" { ($2, $4) }
+  -- TODO: This assumes the ranges are always [hi:lo]; See section 11.5.1!
+  | "[" Expr "+:" Expr "]" { (BinOp Sub (BinOp Add $2 $4) (Number "1"), $2) }
+  | "[" Expr "-:" Expr "]" { ($2, BinOp Add (BinOp Sub $2 $4) (Number "1")) }
 
 LHS :: { LHS }
   : Identifier         { LHSIdent  $1    }