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hacky support for 'part-select addressing'

This commit is contained in:
Zachary Snow 2019-03-30 02:50:45 -04:00
parent abd7ccf49a
commit b45217bae9
1 changed files with 4 additions and 1 deletions
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5
src/Language/SystemVerilog/Parser/Parse.y
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@ -590,7 +590,10 @@ DeclAsgn :: { (Identifier, Expr) }
: Identifier "=" Expr { ($1, $3) } : Identifier "=" Expr { ($1, $3) }
Range :: { Range } Range :: { Range }
: "[" Expr ":" Expr "]" { ($2, $4) } : "[" Expr ":" Expr "]" { ($2, $4) }
-- TODO: This assumes the ranges are always [hi:lo]; See section 11.5.1!
| "[" Expr "+:" Expr "]" { (BinOp Sub (BinOp Add $2 $4) (Number "1"), $2) }
| "[" Expr "-:" Expr "]" { ($2, BinOp Add (BinOp Sub $2 $4) (Number "1")) }
LHS :: { LHS } LHS :: { LHS }
: Identifier { LHSIdent $1 } : Identifier { LHSIdent $1 }