mirror of https://github.com/zachjs/sv2v.git
fix two paramtype edge cases
- don't keep unused template modules even if they are fully-specified - don't reduce modules with unbound type parameters
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@ -77,7 +77,7 @@ convert files =
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|| isntTyped
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|| isUsedAsUntyped
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|| isUsedAsTyped && isInstantiatedViaNonTyped
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|| allTypesHaveDefaults && notInstantiated
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|| allTypesHaveDefaults && notInstantiated && isntTemplateTagged
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where
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maybeTypeMap = Map.lookup name modules
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Just typeMap = maybeTypeMap
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@ -88,6 +88,7 @@ convert files =
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isInstantiatedViaNonTyped = untypedUsageSearch $ Set.singleton name
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allTypesHaveDefaults = all (/= UnknownType) (Map.elems typeMap)
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notInstantiated = lookup name instances == Nothing
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isntTemplateTagged = not $ isTemplateTagged name
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keepDescription _ = True
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-- instantiate the type parameters if this is a used default instance
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@ -99,6 +100,7 @@ convert files =
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where
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shouldntReduce =
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Map.notMember name modules || Map.null typeMap ||
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any (== UnknownType) (Map.elems typeMap) ||
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isTemplateTagged name
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typeMap = modules Map.! name
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rewriteDecl :: Decl -> Decl
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@ -0,0 +1,37 @@
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module mod1;
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parameter type T = logic;
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initial $display("%0d", $bits(T));
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endmodule
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module mod2;
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parameter type T = logic;
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typedef logic [$bits(T) - 1:0] A;
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typedef logic [$bits(A) - 1:0] B;
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mod1 #(A) mA();
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mod1 #(B) mB();
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endmodule
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module mod3;
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parameter type T = logic;
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typedef logic [$bits(T) - 1:0] A;
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typedef logic [$bits(A) - 1:0] B;
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mod2 #(A) mA();
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mod2 #(B) mB();
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endmodule
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module mod4;
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parameter type T = logic;
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typedef logic [$bits(T) - 1:0] A;
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typedef logic [$bits(A) - 1:0] B;
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mod3 #(A) mA();
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mod3 #(B) mB();
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endmodule
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module top;
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typedef struct packed { int a; } X;
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typedef struct packed { int a; X b; } Y;
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typedef logic [$bits(Y) - 1:0] A;
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typedef logic [$bits(A) - 1:0] B;
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mod4 #(A) m4A();
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mod4 #(B) m4B();
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endmodule
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@ -0,0 +1,3 @@
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module top;
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initial repeat (16) $display("%0d", 64);
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endmodule
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@ -0,0 +1,20 @@
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module leaf;
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parameter type T = logic;
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initial #1 $display("leaf: $bits(T)=%0d", $bits(T));
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endmodule
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module intermediate;
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parameter type U = logic;
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parameter W = 4;
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parameter type S = logic [W - 1:0];
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leaf #(S) l();
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initial #2 $display("intermediate: $bits(U)=%0d W=%0d $bits(s)=%0d",
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$bits(U), W, $bits(S));
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endmodule
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module top;
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parameter type B = byte;
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intermediate i1();
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intermediate #(B) i2();
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initial #3 $display("top: $bits(B)=%0d", $bits(B));
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endmodule
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@ -0,0 +1,20 @@
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module leaf;
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parameter T = 1;
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initial #1 $display("leaf: $bits(T)=%0d", T);
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endmodule
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module intermediate;
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parameter U = 1;
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parameter W = 4;
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parameter S = W;
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leaf #(S) l();
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initial #2 $display("intermediate: $bits(U)=%0d W=%0d $bits(s)=%0d",
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U, W, S);
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endmodule
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module top;
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parameter B = 8;
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intermediate i1();
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intermediate #(B) i2();
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initial #3 $display("top: $bits(B)=%0d", B);
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endmodule
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