alias macromodule to module

2020-02-01 16:45:33 -05:00 · 2020-02-01 16:45:33 -05:00 · a402a73477
parent 1a9068409e
commit a402a73477
1 changed files with 1 additions and 0 deletions
--- a/src/Language/SystemVerilog/Parser/Parse.y
+++ b/src/Language/SystemVerilog/Parser/Parse.y
@ -522,6 +522,7 @@ PartHeader :: { [Attr] -> Bool -> PartKW -> [ModuleItem] -> Description }

 ModuleKW :: { PartKW }
  : "module" { Module }
+  | "macromodule" { Module }
 InterfaceKW :: { PartKW }
  : "interface" { Interface }