fix conversion of casts in gen item exprs

src/Convert/Scoper.hs

@@ -349,7 +349,17 @@ evalScoperT declMapper moduleItemMapper genItemMapper stmtMapper topName items =
         -- TODO: This doesn't yet support implicit naming of generate blocks as
         -- blocks as described in Section 27.6.
         fullGenItemMapper :: GenItem -> ScoperT a m GenItem
-        fullGenItemMapper = genItemMapper >=> scopeGenItemMapper
+        fullGenItemMapper genItem = do
+            genItem' <- genItemMapper genItem
+            injected <- gets sInjected
+            if null injected
+                then scopeGenItemMapper genItem'
+                else do
+                    modify' $ \s -> s { sInjected = [] }
+                    injected' <- mapM fullModuleItemMapper injected
+                    genItem'' <- scopeGenItemMapper genItem'
+                    let genItems = map GenModuleItem injected' ++ [genItem'']
+                    return $ GenBlock "" genItems
         scopeGenItemMapper :: GenItem -> ScoperT a m GenItem
         scopeGenItemMapper (GenFor (index, a) b c (GenBlock name genItems)) = do
             enterScope name index

src/Convert/SizeCast.hs

@@ -37,7 +37,7 @@ traverseModuleItemM item =
     traverseExprsM traverseExprM item
 
 traverseGenItemM :: GenItem -> Scoper Type GenItem
-traverseGenItemM = return
+traverseGenItemM = traverseGenItemExprsM traverseExprM
 
 traverseStmtM :: Stmt -> Scoper Type Stmt
 traverseStmtM = traverseStmtExprsM traverseExprM

test/basic/local_cast.sv

@@ -15,5 +15,11 @@ module top;
                 end
             end
         end
+        // TODO: This is not yet supported by iverilog
+        // localparam P = 2;
+        // for (genvar i = 0; i < int'(P); i = i + 1) begin : g
+        //     wire a = i;
+        // end
+        // initial $display("%b %b", g[0].a, g[1].a);
     endgenerate
 endmodule

test/basic/local_cast.v

@@ -20,5 +20,11 @@ module top;
                 cast_i = inp;
             endfunction
         end
+        // TODO: This is not yet supported by iverilog
+        // localparam P = 2;
+        // for (i = 0; i < P; i = i + 1) begin : g
+        //     wire a = i;
+        // end
+        // initial $display("%b %b", g[0].a, g[1].a);
     endgenerate
 endmodule