mirror of https://github.com/zachjs/sv2v.git
flatten tf blocks with decls
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@ -38,9 +38,9 @@ import qualified Convert.SignCast
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import qualified Convert.Simplify
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import qualified Convert.SizeCast
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import qualified Convert.StarPort
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import qualified Convert.StmtBlock
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import qualified Convert.Stream
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import qualified Convert.Struct
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import qualified Convert.TFBlock
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import qualified Convert.Typedef
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import qualified Convert.TypeOf
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import qualified Convert.UnbasedUnsized
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@ -73,9 +73,9 @@ phases excludes =
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, Convert.SizeCast.convert
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, Convert.Simplify.convert
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, Convert.StarPort.convert
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, Convert.StmtBlock.convert
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, Convert.Stream.convert
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, Convert.Struct.convert
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, Convert.TFBlock.convert
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, Convert.Typedef.convert
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, Convert.UnbasedUnsized.convert
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, Convert.Unique.convert
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@ -1,30 +0,0 @@
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{- sv2v
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- Author: Zachary Snow <zach@zachjs.com>
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-
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- Conversion for tasks and functions to use only one statement, as required in
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- Verilog-2005.
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-}
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module Convert.StmtBlock (convert) where
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import Convert.Traverse
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import Language.SystemVerilog.AST
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convert :: [AST] -> [AST]
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convert = map $ traverseDescriptions $ traverseModuleItems convertModuleItem
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convertModuleItem :: ModuleItem -> ModuleItem
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convertModuleItem (MIPackageItem packageItem) =
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MIPackageItem $ convertPackageItem packageItem
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convertModuleItem other = other
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convertPackageItem :: PackageItem -> PackageItem
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convertPackageItem (Function ml t f decls stmts) =
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Function ml t f decls [stmtsToStmt stmts]
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convertPackageItem (Task ml f decls stmts) =
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Task ml f decls [stmtsToStmt stmts]
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convertPackageItem other = other
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stmtsToStmt :: [Stmt] -> Stmt
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stmtsToStmt [stmt] = stmt
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stmtsToStmt stmts = Block Seq "" [] stmts
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@ -0,0 +1,55 @@
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{- sv2v
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- Author: Zachary Snow <zach@zachjs.com>
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-
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- Conversion for tasks and functions to contain only one top-level statement,
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- as required in Verilog-2005. This conversion also hoists data declarations to
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- the task or function level for greater portability.
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-}
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module Convert.TFBlock (convert) where
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import Data.List (isPrefixOf)
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import Convert.Traverse
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import Language.SystemVerilog.AST
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convert :: [AST] -> [AST]
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convert = map $ traverseDescriptions $ traverseModuleItems convertModuleItem
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convertModuleItem :: ModuleItem -> ModuleItem
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convertModuleItem (MIPackageItem packageItem) =
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MIPackageItem $ convertPackageItem packageItem
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convertModuleItem other = other
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convertPackageItem :: PackageItem -> PackageItem
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convertPackageItem (Function ml t f decls stmts) =
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Function ml t f decls' stmts'
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where (decls', stmts') = convertTFBlock decls stmts
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convertPackageItem (Task ml f decls stmts) =
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Task ml f decls' stmts'
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where (decls', stmts') = convertTFBlock decls stmts
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convertPackageItem other = other
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convertTFBlock :: [Decl] -> [Stmt] -> ([Decl], [Stmt])
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convertTFBlock decls stmts =
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(decls', [stmtsToStmt stmts'])
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where (decls', stmts') = flattenOuterBlocks $ Block Seq "" decls stmts
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stmtsToStmt :: [Stmt] -> Stmt
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stmtsToStmt [stmt] = stmt
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stmtsToStmt stmts = Block Seq "" [] stmts
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flattenOuterBlocks :: Stmt -> ([Decl], [Stmt])
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flattenOuterBlocks (Block Seq "" declsA [stmt]) =
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(declsA ++ declsB, stmtsB)
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where (declsB, stmtsB) = flattenOuterBlocks stmt
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flattenOuterBlocks (Block Seq "" declsA (Block Seq name declsB stmtsA : stmtsB)) =
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flattenOuterBlocks $ Block Seq name (declsA ++ declsB) (stmtsA ++ stmtsB)
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flattenOuterBlocks (Block Seq name decls stmts)
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| notscope name = (decls, stmts)
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| otherwise = ([], [Block Seq name decls stmts])
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flattenOuterBlocks stmt = ([], [stmt])
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notscope :: Identifier -> Bool
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notscope "" = True
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notscope name = "sv2v_autoblock_" `isPrefixOf` name
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@ -86,9 +86,9 @@ executable sv2v
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Convert.Simplify
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Convert.SizeCast
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Convert.StarPort
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Convert.StmtBlock
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Convert.Stream
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Convert.Struct
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Convert.TFBlock
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Convert.Traverse
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Convert.Typedef
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Convert.TypeOf
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