luke/sv2v
1
0
Fork 0
mirror of https://github.com/zachjs/sv2v.git synced 2026-09-08 12:53:12 +02:00
Code Issues Packages Projects Releases Wiki Activity

several major fixes surrounding packed arrays

Browse Source 
- entirely new PackedArray conversion (always flattens)
- typedef and struct correctly order packed ranges when combining types
- Stmt LHS traversal no longer traverses nested statements to avoid double conversion
- Logic conversion applies to `initial` blocks`
- new and modified tests to cover these cases
This commit is contained in:
Zachary Snow
2019-04-08 21:28:33 -04:00
parent fb3d68e339
commit 9a38225b1d
14 changed files with 436 additions and 330 deletions
Download Patch File Download Diff File Expand all files Collapse all files
test/basic/flatten.sv
+41 -90
View File
@@ -1,104 +1,55 @@
`define CASE_A(name, dims) \
`define CASE(name, dims, a, b) \
module name(clock, in, out); \
input wire clock, in; \
output logic dims out; \
initial out[0] = 0; \
initial out[1] = 0; \
initial out[2] = 0; \
initial out[0+a] = 0; \
initial out[1+a] = 0; \
initial out[2+a] = 0; \
always @(posedge clock) begin \
/*$display($time, `" name ", out[0+a][1+b+:1]);*/ \
/*$display($time, `" name ", out[0+a][1+b+:1]);*/ \
/*$display($time, `" name ", out[1+a][1+b+:1]);*/ \
/*$display($time, `" name ", out[1+a][1+b+:1]);*/ \
/*$display($time, `" name ", out[2+a][1+b+:1]);*/ \
/*$display($time, `" name ", out[2+a][1+b+:1]);*/ \
\
out[2][4] = out[2][3]; \
out[2][3] = out[2][2]; \
out[2][2] = out[2][1]; \
out[2][1] = out[2][0]; \
out[2][0] = out[1][4]; \
out[2+a][4+b] = out[2+a][3+b]; \
out[2+a][3+b] = out[2+a][2+b]; \
out[2+a][2+b] = out[2+a][1+b]; \
out[2+a][1+b] = out[2+a][0+b]; \
out[2+a][0+b] = out[1+a][4+b]; \
\
out[1][4] = out[1][3]; \
out[1][3] = out[1][2]; \
out[1][2] = out[1][1]; \
out[1][1] = out[1][0]; \
out[1][0] = out[0][4]; \
out[1+a][4+b] = out[1+a][3+b]; \
out[1+a][3+b] = out[1+a][2+b]; \
out[1+a][2+b] = out[1+a][1+b]; \
out[1+a][1+b] = out[1+a][0+b]; \
out[1+a][0+b] = out[0+a][4+b]; \
\
out[0][4] = out[0][3]; \
out[0][3] = out[0][2]; \
out[0][2] = out[0][1]; \
out[0][1] = out[0][0]; \
out[0][0] = in; \
out[0+a][4+b] = out[0+a][3+b]; \
out[0+a][3+b] = out[0+a][2+b]; \
out[0+a][2+b] = out[0+a][1+b]; \
out[0+a][1+b] = out[0+a][0+b]; \
out[0+a][0+b] = in; \
\
end \
endmodule
`CASE_A(A1, [2:0][4:0])
`CASE_A(A2, [0:2][0:4])
`CASE_A(A3, [0:2][4:0])
`CASE_A(A4, [2:0][0:4])
`CASE(A1, [2:0][4:0], 0, 0)
`CASE(A2, [0:2][0:4], 0, 0)
`CASE(A3, [0:2][4:0], 0, 0)
`CASE(A4, [2:0][0:4], 0, 0)
`define CASE_B(name, dims) \
module name(clock, in, out); \
input wire clock, in; \
output logic dims out; \
initial out[1] = 0; \
initial out[2] = 0; \
initial out[3] = 0; \
always @(posedge clock) begin \
\
out[3][5] = out[3][4]; \
out[3][4] = out[3][3]; \
out[3][3] = out[3][2]; \
out[3][2] = out[3][1]; \
out[3][1] = out[2][5]; \
\
out[2][5] = out[2][4]; \
out[2][4] = out[2][3]; \
out[2][3] = out[2][2]; \
out[2][2] = out[2][1]; \
out[2][1] = out[1][5]; \
\
out[1][5] = out[1][4]; \
out[1][4] = out[1][3]; \
out[1][3] = out[1][2]; \
out[1][2] = out[1][1]; \
out[1][1] = in; \
\
end \
endmodule
`CASE(B1, [3:1][5:1], 1, 1)
`CASE(B2, [1:3][1:5], 1, 1)
`CASE(B3, [1:3][5:1], 1, 1)
`CASE(B4, [3:1][1:5], 1, 1)
`CASE_B(B1, [3:1][5:1])
`CASE_B(B2, [1:3][1:5])
`CASE_B(B3, [1:3][5:1])
`CASE_B(B4, [3:1][1:5])
`CASE(C1, [4:2][6:2], 2, 2)
`CASE(C2, [2:4][2:6], 2, 2)
`CASE(C3, [2:4][6:2], 2, 2)
`CASE(C4, [4:2][2:6], 2, 2)
`define CASE_C(name, dims) \
module name(clock, in, out); \
input wire clock, in; \
output logic dims out; \
initial out[2] = 0; \
initial out[3] = 0; \
initial out[4] = 0; \
always @(posedge clock) begin \
\
out[4][6] = out[4][5]; \
out[4][5] = out[4][4]; \
out[4][4] = out[4][3]; \
out[4][3] = out[4][2]; \
out[4][2] = out[3][6]; \
\
out[3][6] = out[3][5]; \
out[3][5] = out[3][4]; \
out[3][4] = out[3][3]; \
out[3][3] = out[3][2]; \
out[3][2] = out[2][6]; \
\
out[2][6] = out[2][5]; \
out[2][5] = out[2][4]; \
out[2][4] = out[2][3]; \
out[2][3] = out[2][2]; \
out[2][2] = in; \
\
end \
endmodule
`CASE_C(C1, [4:2][6:2])
`CASE_C(C2, [2:4][2:6])
`CASE_C(C3, [2:4][6:2])
`CASE_C(C4, [4:2][2:6])
`CASE(D1, [5:3][6:2], 3, 2)
`CASE(D2, [3:5][2:6], 3, 2)
`CASE(D3, [3:5][6:2], 3, 2)
`CASE(D4, [5:3][2:6], 3, 2)
test/basic/flatten_tb.v
+7 -2
View File
@@ -4,9 +4,13 @@
tag``2 tag``two(.clock(clock), .in(in), .out(tag``two_out)); \
tag``3 tag``thr(.clock(clock), .in(in), .out(tag``thr_out)); \
tag``4 tag``fou(.clock(clock), .in(in), .out(tag``fou_out)); \
integer tag``i; \
initial begin \
$monitor(`"tag", $time, ": %h %15b %15b %15b %15b", in, \
tag``one_out, tag``two_out, tag``thr_out, tag``fou_out); \
for (tag``i = 0; tag``i < 20; tag``i++) begin \
#2; \
$display(`"tag", $time, ": %h %15b %15b %15b %15b", in, \
tag``one_out, tag``two_out, tag``thr_out, tag``fou_out); \
end \
end
module top;
@@ -30,5 +34,6 @@ module top;
`FOO(A)
`FOO(B)
`FOO(C)
`FOO(D)
endmodule
test/basic/multipack.sv
+66
View File
@@ -0,0 +1,66 @@
`define PRINT(arr, a, b) \
$display(arr[0+a][0+b]); \
$display(arr[0+a][1+b]); \
$display(arr[0+a][2+b]); \
$display(arr[1+a][0+b]); \
$display(arr[1+a][1+b]); \
$display(arr[1+a][2+b]); \
$display(arr[2+a][0+b]); \
$display(arr[2+a][1+b]); \
$display(arr[2+a][2+b]); \
$display(arr[3+a][0+b]); \
$display(arr[3+a][1+b]); \
$display(arr[3+a][2+b]); \
$display(arr[4+a][0+b]); \
$display(arr[4+a][1+b]); \
$display(arr[4+a][2+b]);
module Example;
typedef logic [2:0] Pack;
Pack [4:0] arr1;
Pack [4:0] arr2;
Pack [4:0] arr3;
initial begin
arr1 = 'b100101010100100;
arr1[0][1] = ~arr1[0][1];
arr1[4][2] = ~arr1[4][2];
`PRINT(arr1, 0, 0)
arr2 = 'b100101000110101;
`PRINT(arr2, 0, 0)
arr3 = 'b100100111101010;
arr3[1] = arr3[2];
`PRINT(arr3, 0, 0)
end
Pack [5:1] arr4;
Pack [5:1] arr5;
Pack [5:1] arr6;
initial begin
arr4 = 'b100101010100100;
arr4[1][1] = ~arr4[1][1];
arr4[5][2] = ~arr4[5][2];
`PRINT(arr4, 1, 0)
arr5 = 'b100101000110101;
`PRINT(arr5, 1, 0)
arr6 = 'b100100111101010;
arr6[2] = arr6[3];
`PRINT(arr6, 1, 0)
end
Pack [1:5] arr7;
Pack [1:5] arr8;
Pack [1:5] arr9;
initial begin
arr7 = 'b100101010100100;
arr7[1][1] = ~arr7[1][1];
arr7[5][2] = ~arr7[5][2];
`PRINT(arr7, 1, 0)
arr8 = 'b100101000110101;
`PRINT(arr8, 1, 0)
arr9 = 'b100100111101010;
arr9[2] = arr9[3];
`PRINT(arr9, 1, 0)
end
endmodule
test/basic/multipack.v
+65
View File
@@ -0,0 +1,65 @@
`define PRINT(arr, a, b) \
$display(arr[0+a][0+b]); \
$display(arr[0+a][1+b]); \
$display(arr[0+a][2+b]); \
$display(arr[1+a][0+b]); \
$display(arr[1+a][1+b]); \
$display(arr[1+a][2+b]); \
$display(arr[2+a][0+b]); \
$display(arr[2+a][1+b]); \
$display(arr[2+a][2+b]); \
$display(arr[3+a][0+b]); \
$display(arr[3+a][1+b]); \
$display(arr[3+a][2+b]); \
$display(arr[4+a][0+b]); \
$display(arr[4+a][1+b]); \
$display(arr[4+a][2+b]);
module Example;
reg [4:0][2:0] arr1;
reg [4:0][2:0] arr2;
reg [4:0][2:0] arr3;
initial begin
arr1 = 'b100101010100100;
arr1[0][1] = ~arr1[0][1];
arr1[4][2] = ~arr1[4][2];
`PRINT(arr1, 0, 0)
arr2 = 'b100101000110101;
`PRINT(arr2, 0, 0)
arr3 = 'b100100111101010;
arr3[1] = arr3[2];
`PRINT(arr3, 0, 0)
end
reg [5:1][2:0] arr4;
reg [5:1][2:0] arr5;
reg [5:1][2:0] arr6;
initial begin
arr4 = 'b100101010100100;
arr4[1][1] = ~arr4[1][1];
arr4[5][2] = ~arr4[5][2];
`PRINT(arr4, 1, 0)
arr5 = 'b100101000110101;
`PRINT(arr5, 1, 0)
arr6 = 'b100100111101010;
arr6[2] = arr6[3];
`PRINT(arr6, 1, 0)
end
reg [1:5][2:0] arr7;
reg [1:5][2:0] arr8;
reg [1:5][2:0] arr9;
initial begin
arr7 = 'b100101010100100;
arr7[1][1] = ~arr7[1][1];
arr7[5][2] = ~arr7[5][2];
`PRINT(arr7, 1, 0)
arr8 = 'b100101000110101;
`PRINT(arr8, 1, 0)
arr9 = 'b100100111101010;
arr9[2] = arr9[3];
`PRINT(arr9, 1, 0)
end
endmodule
test/basic/multipack_tb.v
+3
View File
@@ -0,0 +1,3 @@
module top;
Example example();
endmodule
test/basic/struct_array.sv
+17
View File
@@ -0,0 +1,17 @@
typedef struct packed {
logic x;
logic [3:0] y;
logic [1:0] z;
} Struct_t;
module Unpacker(in, select, a, b, c);
parameter WIDTH = 8;
input Struct_t [WIDTH-1:0] in;
input logic [$clog2(WIDTH)-1:0] select;
output logic a;
output logic [3:0] b;
output logic [1:0] c;
assign a = in[select].x;
assign b = in[select].y;
assign c = in[select].z;
endmodule
test/basic/struct_array.v
+13
View File
@@ -0,0 +1,13 @@
module Unpacker(in, select, a, b, c);
parameter WIDTH = 8;
input wire [WIDTH-1:0][6:0] in;
input wire [$clog2(WIDTH)-1:0] select;
output wire a;
output wire [3:0] b;
output wire [1:0] c;
wire [6:0] p;
assign p = in[select];
assign a = p[6:6];
assign b = p[5:2];
assign c = p[1:0];
endmodule
test/basic/struct_array_tb.v
+34
View File
@@ -0,0 +1,34 @@
module top;
reg [56-1:0] in;
reg [2:0] select;
wire a;
wire [3:0] b;
wire [1:0] c;
Unpacker unpacker(in, select, a, b, c);
initial begin
$monitor("%d: %01b %04b %02b", select, a, b, c);
in = 'b01111011011011101111100111110111001010001011100110101000;
select = 0; #1;
select = 1; #1;
select = 2; #1;
select = 3; #1;
select = 4; #1;
select = 5; #1;
select = 6; #1;
select = 7; #1;
$finish;
end
// 0 1010 00
// 1 1100 11
// 0 1000 10
// 0 1110 01
// 0 0111 11
// 1 0111 11
// 1 0110 11
// 0 1111 01
endmodule