support for flattening multidimensional ports (resolves #21)

src/Convert/PackedArray.hs

@@ -41,9 +41,14 @@ convertDescription =
 
 -- collects and converts multi-dimensional packed-array declarations
 traverseDeclM :: Decl -> State Info Decl
-traverseDeclM (Variable dir t ident a me) = do
+traverseDeclM (Variable Local t ident a me) = do
     t' <- traverseDeclM' t ident
-    return $ Variable dir t' ident a me
+    return $ Variable Local t' ident a me
+traverseDeclM (Variable dir t ident a me) = do
+    let (tf, rs) = typeRanges t
+    let t' = tf $ a ++ rs
+    t'' <- traverseDeclM' t' ident
+    return $ Variable dir t'' ident [] me
 traverseDeclM (Parameter t ident e) = do
     t' <- traverseDeclM' t ident
     return $ Parameter t' ident e

test/basic/multipack_port.sv

@@ -0,0 +1,16 @@
+module foo(clock, data);
+    input logic clock;
+    output logic [10:0] data [5];
+    initial data[0][0] = 0;
+    always @(clock) begin
+        integer i, j;
+        for (i = 4; i >= 0; i--) begin
+            for (j = 9; j >= 0; j--) begin
+                data[i][j + 1] = data[i][j];
+            end
+            if (i != 0)
+                data[i][0] = data[i-1][10];
+        end
+        data[0][0] = ~data[0][0];
+    end
+endmodule

test/basic/multipack_port.v

@@ -0,0 +1,12 @@
+module foo(clock, data);
+    input clock;
+    output reg [54:0] data;
+    initial data[0] = 0;
+    always @(clock) begin : block_name
+        integer i;
+        for (i = 53; i >= 0; i = i - 1) begin
+            data[i+1] = data[i];
+        end
+        data[0] = ~data[0];
+    end
+endmodule

test/basic/multipack_port_tb.v

@@ -0,0 +1,16 @@
+module top;
+    wire [0:54] data;
+    reg clock;
+    foo f(clock, data);
+
+    initial begin
+        clock = 1;
+        forever #1 clock = ~clock;
+    end
+
+    initial begin : foo
+        $monitor("%d %b", $time, data);
+        #100;
+        $finish();
+    end
+endmodule