mirror of https://github.com/zachjs/sv2v.git
unbased unsized conversion refactor
- support ubased unsized bound to ports using injected constants - explicit context-aware literal sizing for complex expressions - fix infinite loop case in NestPI conversion - elaborate size-casts of converted literals
This commit is contained in:
Zachary Snow
parent
1903bc190d
commit
9520894720
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@ -68,7 +68,7 @@ addItems pis existingPIs (item : items) =
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, collectTypesM $ collectNestedTypesM collectTypenamesM
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, collectExprsM $ collectNestedExprsM collectIdentsM
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]
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neededPIs = Set.difference usedPIs existingPIs
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neededPIs = Set.difference (Set.difference usedPIs existingPIs) thisPI
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itemsToAdd = map MIPackageItem $ Map.elems $
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Map.restrictKeys pis neededPIs
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addItems _ _ [] = []
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@ -1,3 +1,4 @@
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{-# LANGUAGE PatternSynonyms #-}
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{- sv2v
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- Author: Zachary Snow <zach@zachjs.com>
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-
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@ -54,6 +55,9 @@ traverseModuleItemM item = traverseExprsM traverseExprM item
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traverseStmtM :: Stmt -> ST Stmt
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traverseStmtM stmt = traverseStmtExprsM traverseExprM stmt
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pattern ConvertedUU :: Char -> Expr
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pattern ConvertedUU ch = Number ['1', '\'', 's', 'b', ch]
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traverseExprM :: Expr -> ST Expr
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traverseExprM =
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traverseNestedExprsM convertExprM
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@ -85,6 +89,13 @@ traverseExprM =
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convertExprM other = return other
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convertCastM :: Expr -> Expr -> ST Expr
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convertCastM (s @ (Number str)) (e @ (ConvertedUU ch)) = do
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typeMap <- get
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case (exprSigning typeMap e, readNumber str) of
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(Just Unspecified, Just n) -> return $ Number $
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show n ++ "'b" ++ take (fromIntegral n) (repeat ch)
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(Just sg, _) -> convertCastWithSigningM s e sg
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_ -> return $ Cast (Right s) e
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convertCastM s e = do
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typeMap <- get
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case exprSigning typeMap e of
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@ -1,74 +1,241 @@
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{-# LANGUAGE PatternSynonyms #-}
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{- sv2v
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- Author: Zachary Snow <zach@zachjs.com>
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-
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- Conversion for unbased, unsized literals ('0, '1, 'z, 'x)
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-
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- The literals are given a binary base and are made signed to allow sign
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- extension. This enables the desired implicit casting in Verilog-2005.
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- However, in self-determined contextes, the literals are given an explicit
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- size of 1.
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- The literals are given a binary base, a size of 1, and are made signed to
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- allow sign extension. For context-determined expressions, the converted
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- literals are explicitly cast to the appropriate context-determined size.
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-
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- As a special case, unbased, unsized literals which take on the size of a
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- module port binding are replaced with a hierarchical reference to an
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- appropriately sized constant which is injected into the instantiated module's
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- definition. This allows these literals to be used for parameterized ports
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- without further complicating other conversions, as hierarchical references
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- are not allowed within constant expressions.
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-}
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module Convert.UnbasedUnsized (convert) where
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import Control.Monad.Writer
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import Convert.Traverse
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import Language.SystemVerilog.AST
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data ExprContext
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= SelfDetermined
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| ContextDetermined Expr
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deriving (Eq, Show)
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type Port = Either Identifier Int
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data Bind = Bind
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{ bModule :: Identifier
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, bBit :: Char
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, bPort :: Port
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} deriving (Eq, Show)
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type Binds = [Bind]
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convert :: [AST] -> [AST]
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convert = map $ traverseDescriptions $ traverseModuleItems convertModuleItem
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convert files =
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map (traverseDescriptions $ convertDescription binds) files'
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where
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(files', binds) = runWriter $
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mapM (mapM $ traverseModuleItemsM convertModuleItemM) files
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convertDescription :: Binds -> Description -> Description
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convertDescription [] other = other
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convertDescription binds (Part attrs extern kw lifetime name ports items) =
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Part attrs extern kw lifetime name ports items'
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where
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binds' = filter ((== name) . bModule) binds
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items' = removeDupes [] $ items ++ map (bindItem ports) binds'
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removeDupes :: [Identifier] -> [ModuleItem] -> [ModuleItem]
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removeDupes _ [] = []
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removeDupes existing (item @ (MIPackageItem (Decl decl)) : is) =
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case decl of
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Param Localparam _ x _ ->
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if elem x existing
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then removeDupes existing is
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else item : removeDupes (x : existing) is
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_ -> item : removeDupes existing is
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removeDupes existing (item : is) =
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item : removeDupes existing is
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convertDescription _ other = other
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bindName :: Bind -> Identifier
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bindName (Bind _ ch (Left x)) = "sv2v_uub_" ++ ch : '_' : x
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bindName (Bind m ch (Right i)) =
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bindName $ Bind m ch (Left $ show i)
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bindItem :: [Identifier] -> Bind -> ModuleItem
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bindItem ports bind =
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MIPackageItem $ Decl $ Param Localparam typ name expr
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where
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portName = lookupPort ports (bPort bind)
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size = DimsFn FnBits $ Right $ Ident portName
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rng = (BinOp Sub size (Number "1"), Number "0")
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typ = Implicit Unspecified [rng]
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name = bindName bind
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expr = literalFor $ bBit bind
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lookupPort :: [Identifier] -> Port -> Identifier
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lookupPort _ (Left x) = x
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lookupPort ports (Right i) =
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if i < length ports
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then ports !! i
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else error $ "out of bounds bort binding " ++ show (ports, i)
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convertModuleItemM :: ModuleItem -> Writer Binds ModuleItem
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convertModuleItemM (Instance moduleName params instanceName [] bindings) = do
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bindings' <- mapM (uncurry convertBinding) $ zip bindings [0..]
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let item = Instance moduleName params instanceName [] bindings'
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return $ convertModuleItem item
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where
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tag = Ident ":uub:"
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convertBinding :: PortBinding -> Int -> Writer Binds PortBinding
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convertBinding (portName, expr) idx = do
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let port = if null portName then Right idx else Left portName
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let expr' = convertExpr (ContextDetermined tag) expr
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expr'' <- traverseNestedExprsM (replaceBindingExpr port) expr'
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return (portName, expr'')
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replaceBindingExpr :: Port -> Expr -> Writer Binds Expr
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replaceBindingExpr port (orig @ (Cast Right{} (Number num))) = do
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let ch = last num
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if orig == sizedLiteralFor tag ch
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then do
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let bind = Bind moduleName ch port
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tell [bind]
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let expr = Dot (Ident instanceName) (bindName bind)
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return expr
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else return orig
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replaceBindingExpr _ other = return other
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convertModuleItemM other = return $ convertModuleItem other
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convertModuleItem :: ModuleItem -> ModuleItem
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convertModuleItem =
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traverseExprs (traverseNestedExprs convertExpr) .
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traverseStmts (traverseNestedStmts convertStmt) .
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traverseTypes (traverseNestedTypes convertType)
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traverseExprs (convertExpr SelfDetermined) .
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traverseTypes (traverseNestedTypes convertType) .
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traverseAsgns convertAsgn
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digits :: [Char]
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digits = ['0', '1', 'x', 'z', 'X', 'Z']
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literalFor :: String -> Char -> Expr
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literalFor prefix ch =
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literalFor :: Char -> Expr
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literalFor ch =
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if elem ch digits
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then Number (prefix ++ [ch])
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then Number ("1'sb" ++ [ch])
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else error $ "unexpected unbased-unsized digit: " ++ [ch]
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sizedLiteralFor :: Char -> Expr
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sizedLiteralFor = literalFor "1'sb"
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sizedLiteralFor :: Expr -> Char -> Expr
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sizedLiteralFor expr ch =
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Cast (Right size) (literalFor ch)
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where size = DimsFn FnBits $ Right expr
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unsizedLiteralFor :: Char -> Expr
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unsizedLiteralFor '1' = UniOp UniSub $ Number "'sd1"
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unsizedLiteralFor ch = literalFor "'sd" ch
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convertAsgn :: (LHS, Expr) -> (LHS, Expr)
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convertAsgn (lhs, expr) =
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(lhs, convertExpr context expr)
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where context = ContextDetermined $ lhsToExpr lhs
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convertExpr :: Expr -> Expr
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convertExpr (DimsFn fn (Right e)) =
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DimsFn fn $ Right $ convertSizeExpr e
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convertExpr (Concat exprs) =
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Concat $ map convertSelfDeterminedExpr exprs
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convertExpr (Repeat count exprs) =
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Repeat count $ map convertSelfDeterminedExpr exprs
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convertExpr (Number ['\'', ch]) =
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unsizedLiteralFor ch
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convertExpr other = other
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convertExpr :: ExprContext -> Expr -> Expr
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convertExpr _ (DimsFn fn (Right e)) =
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DimsFn fn $ Right $ convertExpr SelfDetermined e
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convertExpr _ (Cast te e) =
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Cast te $ convertExpr SelfDetermined e
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convertExpr _ (Concat exprs) =
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Concat $ map (convertExpr SelfDetermined) exprs
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convertExpr _ (Pattern items) =
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Pattern $ zip
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(map fst items)
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(map (convertExpr SelfDetermined . snd) items)
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convertExpr _ (Call expr (Args pnArgs kwArgs)) =
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Call expr $ Args pnArgs' kwArgs'
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where
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pnArgs' = map (convertExpr SelfDetermined) pnArgs
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Pattern kwArgs' = convertExpr SelfDetermined $ Pattern kwArgs
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convertExpr _ (Repeat count exprs) =
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Repeat count $ map (convertExpr SelfDetermined) exprs
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convertExpr SelfDetermined (Mux cond (e1 @ UU{}) (e2 @ UU{})) =
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Mux
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(convertExpr SelfDetermined cond)
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(convertExpr SelfDetermined e1)
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(convertExpr SelfDetermined e2)
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convertExpr SelfDetermined (Mux cond e1 e2) =
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Mux
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(convertExpr SelfDetermined cond)
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(convertExpr (ContextDetermined e2) e1)
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(convertExpr (ContextDetermined e1) e2)
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convertExpr (ContextDetermined expr) (Mux cond e1 e2) =
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Mux
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(convertExpr SelfDetermined cond)
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(convertExpr context e1)
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(convertExpr context e2)
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where context = ContextDetermined expr
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convertExpr SelfDetermined (BinOp op e1 e2) =
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if isPeerSizedBinOp op || isParentSizedBinOp op
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then BinOp op
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(convertExpr (ContextDetermined e2) e1)
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(convertExpr (ContextDetermined e1) e2)
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else BinOp op
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(convertExpr SelfDetermined e1)
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(convertExpr SelfDetermined e2)
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convertExpr (ContextDetermined expr) (BinOp op e1 e2) =
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if isPeerSizedBinOp op then
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BinOp op
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(convertExpr (ContextDetermined e2) e1)
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(convertExpr (ContextDetermined e1) e2)
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else if isParentSizedBinOp op then
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BinOp op
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(convertExpr context e1)
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(convertExpr context e2)
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else
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BinOp op
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(convertExpr SelfDetermined e1)
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(convertExpr SelfDetermined e2)
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where context = ContextDetermined expr
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convertExpr context (UniOp op expr) =
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if isSizedUniOp op
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then UniOp op (convertExpr context expr)
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else UniOp op (convertExpr SelfDetermined expr)
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convertExpr SelfDetermined (UU ch) =
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literalFor ch
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convertExpr (ContextDetermined expr) (UU ch) =
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sizedLiteralFor expr ch
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convertExpr _ other = other
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convertSelfDeterminedExpr :: Expr -> Expr
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convertSelfDeterminedExpr (Number ['\'', ch]) =
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sizedLiteralFor ch
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convertSelfDeterminedExpr other = other
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convertStmt :: Stmt -> Stmt
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convertStmt (Subroutine (fn @ (Ident ('$' : _))) (Args args [])) =
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Subroutine fn (Args args' [])
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where args' = map convertSelfDeterminedExpr args
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convertStmt other = other
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pattern UU :: Char -> Expr
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pattern UU ch = Number ['\'', ch]
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convertType :: Type -> Type
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convertType (TypeOf e) = TypeOf $ convertSizeExpr e
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convertType (TypeOf e) = TypeOf $ convertExpr SelfDetermined e
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convertType other = other
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convertSizeExpr :: Expr -> Expr
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convertSizeExpr (Mux cond e1 e2) =
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Mux cond e1' e2'
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where
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e1' = convertSelfDeterminedExpr e1
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e2' = convertSelfDeterminedExpr e2
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convertSizeExpr e = convertSelfDeterminedExpr e
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isParentSizedBinOp :: BinOp -> Bool
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isParentSizedBinOp BitAnd = True
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isParentSizedBinOp BitXor = True
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isParentSizedBinOp BitXnor = True
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isParentSizedBinOp BitOr = True
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isParentSizedBinOp Mul = True
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isParentSizedBinOp Div = True
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isParentSizedBinOp Mod = True
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isParentSizedBinOp Add = True
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isParentSizedBinOp Sub = True
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isParentSizedBinOp _ = False
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isPeerSizedBinOp :: BinOp -> Bool
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isPeerSizedBinOp Eq = True
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isPeerSizedBinOp Ne = True
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isPeerSizedBinOp TEq = True
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isPeerSizedBinOp TNe = True
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isPeerSizedBinOp WEq = True
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isPeerSizedBinOp WNe = True
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isPeerSizedBinOp Lt = True
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isPeerSizedBinOp Le = True
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isPeerSizedBinOp Gt = True
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isPeerSizedBinOp Ge = True
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isPeerSizedBinOp _ = False
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isSizedUniOp :: UniOp -> Bool
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isSizedUniOp = (/= LogNot)
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@ -1,6 +1,6 @@
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`define TEST(value) \
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logic [63:0] val_``value = 'value; \
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initial $display(`"'value -> %b (%0d) %b (%0d)", \
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initial $display(`"'value -> %b (%0d) %b (%0d)`", \
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val_``value, $bits(val_``value), \
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'value, $bits('value) \
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);
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@ -46,4 +46,69 @@ module top;
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$display($bits(type('1)));
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$display($bits(type(flag ? '1 : 'x)));
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end
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parameter P = 1;
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M m1('0, '1, 'x, 'z);
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M #( 2) m2('0, '1, 'x, 'z);
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M #(28) m3('0, '1, 'x, 'z);
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M #(29) m4('0, '1, 'x, 'z);
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M #(30) m5('0, '1, 'x, 'z);
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M #(31) m6('0, '1, 'x, 'z);
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M #(32) m7('0, '1, 'x, 'z);
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M #(33) m8('0, '1, 'x, 'z);
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M #(34) m9('0, '1, 'x, 'z);
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M #(31) mA(P ? '0 : '1, !P ? '0 : '1, 'x, 'z);
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M #(34) mB(P ? '0 : '1, !P ? '0 : '1, 'x, 'z);
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M #(31) mC(P ? '0 : '0 + '1, !P ? '0 : '0 + '1, 'x, 'z);
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M #(34) mD(P ? '0 : '0 + '1, !P ? '0 : '0 + '1, 'x, 'z);
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`define TEST_OP(left, op, right, expected) \
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$display(`"%s: (left) op (right) -> %b (ref: %b)`", \
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((left) op (right)) == expected ? "PASS" : "FAIL", \
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(left) op (right), expected \
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);
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initial begin
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`TEST_OP( 1'h1 , ==, '1, 1'b1)
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`TEST_OP( 2'h3 , ==, '1, 1'b1)
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`TEST_OP(31'h7fffffff , ==, '1, 1'b1)
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`TEST_OP(32'hffffffff , ==, '1, 1'b1)
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`TEST_OP(33'h1ffffffff, ==, '1, 1'b1)
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`TEST_OP( 1'h1 , <=, '1, 1'b1)
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`TEST_OP( 2'h3 , <=, '1, 1'b1)
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`TEST_OP(31'h7fffffff , <=, '1, 1'b1)
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`TEST_OP(32'hffffffff , <=, '1, 1'b1)
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`TEST_OP(33'h1ffffffff, <=, '1, 1'b1)
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`TEST_OP( 1'h1 , >=, '1, 1'b1)
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`TEST_OP( 2'h3 , >=, '1, 1'b1)
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`TEST_OP(31'h7fffffff , >=, '1, 1'b1)
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`TEST_OP(32'hffffffff , >=, '1, 1'b1)
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`TEST_OP(33'h1ffffffff, >=, '1, 1'b1)
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`TEST_OP( 1'h1 , &, '1, 1'h1 )
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`TEST_OP( 2'h3 , &, '1, 2'h3 )
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`TEST_OP(31'h7fffffff , &, '1, 31'h7fffffff )
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`TEST_OP(32'hffffffff , &, '1, 32'hffffffff )
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`TEST_OP(33'h1ffffffff, &, '1, 33'h1ffffffff)
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`TEST_OP(33'h1ffffffff, &, P ? '1 : '0, 33'h1ffffffff)
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`TEST_OP(33'h1ffffffff, &, '1 & '1, 33'h1ffffffff)
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`TEST_OP(33'h1ffffffff, &, !P ? '1 : '0 - 1, 33'h1ffffffff)
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`TEST_OP(34'h3ffffffff, &, '0 - 1, 34'h3ffffffff)
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`TEST_OP(1, ==, 2'h3 == '1, 1'b1)
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end
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endmodule
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module M(a, b, c, d);
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parameter W = 1;
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input logic [W+0:1] a;
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input logic [W+1:1] b;
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input logic [W+2:1] c;
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input logic [W+3:1] d;
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initial $display("M W=%0d %b %b %b %b", W, a, b, c, d);
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endmodule
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@ -1,6 +1,6 @@
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`define TEST(value) \
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wire [63:0] val_``value = {64{1'b``value}}; \
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initial $display(`"'value -> %b (%0d) %b (%0d)", \
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initial $display(`"'value -> %b (%0d) %b (%0d)`", \
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val_``value, $bits(val_``value), \
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1'b``value, $bits(1'b``value) \
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);
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@ -25,7 +25,7 @@ module top;
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flag = 1;
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a = (flag ? 32'hFFFFFFFF : i);
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b = (flag ? 32'hXXXXXXXX : i);
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c = (flag ? 32'hFFFFFFFF: i);
|
||||
c = (flag ? 32'hFFFFFFFF : i);
|
||||
d = (flag ? 64'hFFFFFFFFFFFFFFFF : j);
|
||||
e = (flag ? 64'hXXXXXXXXXXXXXXXX : j);
|
||||
$display("%b", a);
|
||||
|
|
@ -46,4 +46,64 @@ module top;
|
|||
$display(1);
|
||||
$display(1);
|
||||
end
|
||||
|
||||
M m1({ 1 {1'b0}}, { 2 {1'b1}}, { 3 {1'bx}}, { 4 {1'bz}});
|
||||
M #( 2) m2({ 2 {1'b0}}, { 3 {1'b1}}, { 4 {1'bx}}, { 5 {1'bz}});
|
||||
M #(28) m3({28 {1'b0}}, {29 {1'b1}}, {30 {1'bx}}, {31 {1'bz}});
|
||||
M #(29) m4({29 {1'b0}}, {30 {1'b1}}, {31 {1'bx}}, {32 {1'bz}});
|
||||
M #(30) m5({30 {1'b0}}, {31 {1'b1}}, {32 {1'bx}}, {33 {1'bz}});
|
||||
M #(31) m6({31 {1'b0}}, {32 {1'b1}}, {33 {1'bx}}, {34 {1'bz}});
|
||||
M #(32) m7({32 {1'b0}}, {33 {1'b1}}, {34 {1'bx}}, {35 {1'bz}});
|
||||
M #(33) m8({33 {1'b0}}, {34 {1'b1}}, {35 {1'bx}}, {36 {1'bz}});
|
||||
M #(34) m9({34 {1'b0}}, {35 {1'b1}}, {36 {1'bx}}, {37 {1'bz}});
|
||||
|
||||
M #(31) mA({31 {1'b0}}, {32 {1'b1}}, {33 {1'bx}}, {34 {1'bz}});
|
||||
M #(34) mB({34 {1'b0}}, {35 {1'b1}}, {36 {1'bx}}, {37 {1'bz}});
|
||||
M #(31) mC({31 {1'b0}}, {32 {1'b1}}, {33 {1'bx}}, {34 {1'bz}});
|
||||
M #(34) mD({34 {1'b0}}, {35 {1'b1}}, {36 {1'bx}}, {37 {1'bz}});
|
||||
|
||||
`define TEST_OP(left, op, right, expected) \
|
||||
$display(`"PASS: (left) op (right) -> %b (ref: %b)`", expected, expected);
|
||||
|
||||
initial begin
|
||||
`TEST_OP( 1'h1 , ==, '1, 1'b1)
|
||||
`TEST_OP( 2'h3 , ==, '1, 1'b1)
|
||||
`TEST_OP(31'h7fffffff , ==, '1, 1'b1)
|
||||
`TEST_OP(32'hffffffff , ==, '1, 1'b1)
|
||||
`TEST_OP(33'h1ffffffff, ==, '1, 1'b1)
|
||||
|
||||
`TEST_OP( 1'h1 , <=, '1, 1'b1)
|
||||
`TEST_OP( 2'h3 , <=, '1, 1'b1)
|
||||
`TEST_OP(31'h7fffffff , <=, '1, 1'b1)
|
||||
`TEST_OP(32'hffffffff , <=, '1, 1'b1)
|
||||
`TEST_OP(33'h1ffffffff, <=, '1, 1'b1)
|
||||
|
||||
`TEST_OP( 1'h1 , >=, '1, 1'b1)
|
||||
`TEST_OP( 2'h3 , >=, '1, 1'b1)
|
||||
`TEST_OP(31'h7fffffff , >=, '1, 1'b1)
|
||||
`TEST_OP(32'hffffffff , >=, '1, 1'b1)
|
||||
`TEST_OP(33'h1ffffffff, >=, '1, 1'b1)
|
||||
|
||||
`TEST_OP( 1'h1 , &, '1, 1'h1 )
|
||||
`TEST_OP( 2'h3 , &, '1, 2'h3 )
|
||||
`TEST_OP(31'h7fffffff , &, '1, 31'h7fffffff )
|
||||
`TEST_OP(32'hffffffff , &, '1, 32'hffffffff )
|
||||
`TEST_OP(33'h1ffffffff, &, '1, 33'h1ffffffff)
|
||||
|
||||
`TEST_OP(33'h1ffffffff, &, P ? '1 : '0, 33'h1ffffffff)
|
||||
`TEST_OP(33'h1ffffffff, &, '1 & '1, 33'h1ffffffff)
|
||||
`TEST_OP(33'h1ffffffff, &, !P ? '1 : '0 - 1, 33'h1ffffffff)
|
||||
`TEST_OP(34'h3ffffffff, &, '0 - 1, 34'h3ffffffff)
|
||||
|
||||
`TEST_OP(1, ==, 2'h3 == '1, 1'b1)
|
||||
end
|
||||
endmodule
|
||||
|
||||
module M(a, b, c, d);
|
||||
parameter W = 1;
|
||||
input wire [W+0:1] a;
|
||||
input wire [W+1:1] b;
|
||||
input wire [W+2:1] c;
|
||||
input wire [W+3:1] d;
|
||||
initial $display("M W=%0d %b %b %b %b", W, a, b, c, d);
|
||||
endmodule
|
||||
|
|
|
|||
Loading…
Reference in New Issue