mirror of https://github.com/zachjs/sv2v.git
cleaned up command line args module a bit
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@ -7,7 +7,7 @@
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module Convert (convert) where
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module Convert (convert) where
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import Language.SystemVerilog.AST
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import Language.SystemVerilog.AST
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import qualified Args as Args
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import Job (Target(..))
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import qualified Convert.AlwaysKW
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import qualified Convert.AlwaysKW
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import qualified Convert.CaseKW
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import qualified Convert.CaseKW
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@ -19,24 +19,24 @@ import qualified Convert.StarPort
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type Phase = AST -> AST
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type Phase = AST -> AST
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phases :: Args.Target -> [Phase]
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phases :: Target -> [Phase]
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phases Args.YOSYS =
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phases YOSYS =
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[ Convert.Typedef.convert
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[ Convert.Typedef.convert
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, Convert.PackedArray.convert
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, Convert.PackedArray.convert
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, Convert.StarPort.convert
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, Convert.StarPort.convert
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]
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]
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phases Args.VTR =
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phases VTR =
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(phases Args.YOSYS) ++
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(phases YOSYS) ++
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[ Convert.AlwaysKW.convert
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[ Convert.AlwaysKW.convert
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, Convert.CaseKW.convert
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, Convert.CaseKW.convert
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, Convert.Logic.convert
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, Convert.Logic.convert
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, Convert.SplitPortDecl.convert
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, Convert.SplitPortDecl.convert
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]
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]
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run :: Args.Target -> Phase
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run :: Target -> Phase
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run target = foldr (.) id $ phases target
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run target = foldr (.) id $ phases target
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convert :: Args.Target -> Phase
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convert :: Target -> Phase
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convert target = convert'
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convert target = convert'
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where
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where
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convert' :: Phase
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convert' :: Phase
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@ -5,7 +5,7 @@
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- Command line arguments.
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- Command line arguments.
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-}
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-}
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module Args where
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module Job where
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import System.Console.CmdArgs
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import System.Console.CmdArgs
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@ -28,5 +28,5 @@ defaultJob = Job
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&= details [ "sv2v converts SystemVerilog to Verilog."
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&= details [ "sv2v converts SystemVerilog to Verilog."
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, "More info: https://github.com/zachjs/sv2v" ]
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, "More info: https://github.com/zachjs/sv2v" ]
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readArgs :: IO Job
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readJob :: IO Job
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readArgs = cmdArgs defaultJob
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readJob = cmdArgs defaultJob
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19
src/sv2v.hs
19
src/sv2v.hs
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@ -1,4 +1,3 @@
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{-# LANGUAGE DeriveDataTypeable #-}
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{- sv2v
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{- sv2v
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- Author: Zachary Snow <zach@zachjs.com>
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- Author: Zachary Snow <zach@zachjs.com>
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-
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-
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@ -8,21 +7,19 @@
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import System.IO
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import System.IO
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import System.Exit
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import System.Exit
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import Args (readArgs, target, file)
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import Job (readJob, file, target)
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import Convert (convert)
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import Convert (convert)
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import Language.SystemVerilog.Parser
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import Language.SystemVerilog.Parser
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main :: IO ()
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main :: IO ()
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main = do
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main = do
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args <- readArgs
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job <- readJob
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let filePath = file args
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-- parse the input file
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let filePath = file job
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content <- readFile filePath
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content <- readFile filePath
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let ast = parseFile [] filePath content
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let ast = parseFile [] filePath content
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let res = Right (convert (target args) ast)
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-- convert the file
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case res of
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let ast' = convert (target job) ast
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Left _ -> do
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-- print the converted file out
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--hPrint stderr err
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hPrint stdout ast'
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exitFailure
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Right str -> do
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hPrint stdout str
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exitSuccess
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exitSuccess
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@ -48,7 +48,7 @@ executable sv2v
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Convert.Typedef
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Convert.Typedef
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Convert.Traverse
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Convert.Traverse
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-- sv2v CLI modules
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-- sv2v CLI modules
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Args
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Job
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ghc-options:
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ghc-options:
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-O3
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-O3
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-threaded
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-threaded
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