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restrict implicit logic to output ports

This commit is contained in:
Zachary Snow 2021-09-07 13:06:24 -04:00
parent 598b4260b6
commit 88d632fb14
1 changed files with 3 additions and 3 deletions
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6
src/Convert/PortDecl.hs
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@ -81,9 +81,9 @@ convertTFDecls =
-- given helpfully extracted information, update the given declaration -- given helpfully extracted information, update the given declaration
rewrite :: Decl -> Maybe Decl -> Direction -> Identifier -> Expr -> ModuleItem rewrite :: Decl -> Maybe Decl -> Direction -> Identifier -> Expr -> ModuleItem
-- implicitly-typed ports default to `logic` in SystemVerilog -- implicitly-typed output ports default to `logic` in SystemVerilog
rewrite (Variable d (Implicit sg rs) x a e) Nothing _ _ _ = rewrite (Variable Output (Implicit sg rs) x a e) Nothing _ _ _ =
MIPackageItem $ Decl $ Variable d (IntegerVector TLogic sg rs) x a e MIPackageItem $ Decl $ Variable Output (IntegerVector TLogic sg rs) x a e
-- not a relevant port declaration -- not a relevant port declaration
rewrite decl Nothing _ _ _ = rewrite decl Nothing _ _ _ =
MIPackageItem $ Decl decl MIPackageItem $ Decl decl