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support for ++ and -- as bare Stmts

This commit is contained in:
Zachary Snow 2019-03-28 15:08:05 -04:00
parent 69a5585a7f
commit 848f8cbd61
1 changed files with 2 additions and 0 deletions
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2
src/Language/SystemVerilog/Parser/Parse.y
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@ -543,6 +543,8 @@ Stmt :: { Stmt }
| LHS AsgnOp Expr ";" { AsgnBlk $2 $1 $3 }
| Identifier ";" { Subroutine $1 [] }
| LHS "<=" opt(DelayOrEventControl) Expr ";" { Asgn $3 $1 $4 }
| LHS IncOrDecOperator ";" { AsgnBlk (AsgnOp $2) $1 (Number "1") }
| IncOrDecOperator LHS ";" { AsgnBlk (AsgnOp $1) $2 (Number "1") }
StmtNonAsgn :: { Stmt }
: ";" { Null }
| "begin" opt(Tag) DeclsAndStmts "end" opt(Tag) { Block (combineTags $2 $5) (fst $3) (snd $3) }