mirror of https://github.com/zachjs/sv2v.git
added test coverage for compilation unit package resolution
This commit is contained in:
Zachary Snow
parent
9c160c3d20
commit
8119cdd6b1
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@ -0,0 +1,125 @@
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#!/bin/bash
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SCRIPT_DIR=`dirname "${BASH_SOURCE[0]}"`
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SV2V="$SCRIPT_DIR/../../bin/sv2v"
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assertExists() {
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file=$1
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[ -f "$file" ]
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assertTrue "$file does not exist" $?
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}
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# USAGE: simulate <vcd-file> <log-file> <top-module> <file> [<file> ...]
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simulate() {
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# arguments
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sim_vcd="$1"; shift
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sim_log="$1"; shift
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sim_top="$1"; shift
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# compile the files
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sim_prog="$SHUNIT_TMPDIR/simprog.exe"
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iv_output=`iverilog \
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-Wall \
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-Wno-select-range \
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-o "$sim_prog" \
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-g2005 \
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-DTEST_VCD="\"$sim_vcd\"" \
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-DTEST_TOP=$sim_top \
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"$SCRIPT_DIR/tb_dumper.v" \
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"$@" 2>&1`
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assertTrue "iverilog on $1 failed" $?
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assertNull "iverilog emitted warnings:" "$iv_output"
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if [ "$iv_output" != "" ]; then
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echo "$iv_output"
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fi
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# run the simulation
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$sim_prog > $sim_log
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assertTrue "simulating $1 failed" $?
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# remove the date from the VCD
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sed -i.orig -e "1,3d" "$sim_vcd"
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# remove the "opened file..." prompt from the log
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sed -i.orig -e "1,1d" "$sim_log"
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}
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assertConverts() {
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ac_file="$1"
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ac_tmpa="$SHUNIT_TMPDIR/ac-conv-tmpa.v"
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ac_tmpb="$SHUNIT_TMPDIR/ac-conv-tmpb.v"
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ac_tmpc="$SHUNIT_TMPDIR/ac-conv-tmpc.v"
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$SV2V "$ac_file" 2> /dev/null > "$ac_tmpa"
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assertTrue "1st conversion of $ac_file failed" $?
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$SV2V "$ac_tmpa" 2> /dev/null > "$ac_tmpb"
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assertTrue "2nd conversion of $ac_file failed" $?
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$SV2V "$ac_tmpb" 2> /dev/null > "$ac_tmpc"
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assertTrue "3rd conversion of $ac_file failed" $?
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diff "$ac_tmpb" "$ac_tmpc" > /dev/null
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assertTrue "conversion of $ac_file not stable after the second iteration" $?
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# using sed to remove quoted strings
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filtered=`sed -E 's/"([^"]|\")+"//g' "$ac_tmpa"`
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echo "$filtered" | grep "\$bits" > /dev/null
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assertFalse "conversion of $ac_file still contains \$bits" $?
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echo "$filtered" | grep "\]\[" > /dev/null
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assertFalse "conversion of $ac_file still contains multi-dim arrays" $?
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echo "$filtered" | egrep "\s(int\|bit\|logic\|byte\|struct\|enum\|longint\|shortint)\s"
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assertFalse "conversion of $ac_file still contains SV types" $?
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}
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# convert SystemVerilog source file(s)
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convert() {
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out_file="$1"; shift
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$SV2V "$@" 2> /dev/null > "$out_file"
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assertTrue "conversion failed" $?
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assertExists "$out_file"
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}
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simpleTest() {
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sv="$1"
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ve="$2"
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tb="$3"
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assertNotNull "SystemVerilog file not specified" $sv
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assertNotNull "Verilog file not specified" $ve
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assertNotNull "Testbench not specified" $tb
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# some tests don't have a separate testbench, instead having the top-level
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# module defined in both of the input files
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if [ ! -f "$tb" ]; then
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tb="$SCRIPT_DIR/empty.v"
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fi
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assertExists $sv
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assertExists $ve
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assertExists $tb
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assertConverts "$sv"
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assertConverts "$ve"
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assertConverts "$tb"
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cv="$SHUNIT_TMPDIR/conv.v"
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convert "$cv" "$sv"
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simulateAndCompare "$ve" "$cv" "$tb"
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}
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simulateAndCompare() {
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ve="$1"
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cv="$2"
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tb="$3"
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ref_vcd="$SHUNIT_TMPDIR/ref.vcd"
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gen_vcd="$SHUNIT_TMPDIR/gen.vcd"
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ref_log="$SHUNIT_TMPDIR/ref.log"
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gen_log="$SHUNIT_TMPDIR/gen.log"
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# simulate and compare the two files
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simulate "$ref_vcd" "$ref_log" top "$ve" "$tb"
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simulate "$gen_vcd" "$gen_log" top "$cv" "$tb"
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diff "$ref_vcd" "$gen_vcd" > /dev/null
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assertTrue "VCDs are different" $?
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output=`diff "$ref_log" "$gen_log"`
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assertTrue "Simulation outputs differ:\n$output" $?
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}
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runTest() {
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test="$1"
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simpleTest "${test}.sv" "${test}.v" "${test}_tb.v"
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}
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@ -1,115 +1,6 @@
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#!/bin/bash
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SCRIPT_DIR=`dirname "${BASH_SOURCE[0]}"`
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SV2V="$SCRIPT_DIR/../../bin/sv2v"
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assertExists() {
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file=$1
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[ -f "$file" ]
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assertTrue "$file does not exist" $?
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}
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# USAGE: simulate <vcd-file> <log-file> <top-module> <file> [<file> ...]
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simulate() {
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# arguments
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sim_vcd="$1"; shift
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sim_log="$1"; shift
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sim_top="$1"; shift
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# compile the files
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sim_prog="$SHUNIT_TMPDIR/simprog.exe"
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iv_output=`iverilog \
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-Wall \
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-Wno-select-range \
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-o "$sim_prog" \
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-g2005 \
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-DTEST_VCD="\"$sim_vcd\"" \
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-DTEST_TOP=$sim_top \
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"$SCRIPT_DIR/tb_dumper.v" \
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"$@" 2>&1`
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assertTrue "iverilog on $1 failed" $?
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assertNull "iverilog emitted warnings:" "$iv_output"
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if [ "$iv_output" != "" ]; then
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echo "$iv_output"
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fi
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# run the simulation
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$sim_prog > $sim_log
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assertTrue "simulating $1 failed" $?
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# remove the date from the VCD
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sed -i.orig -e "1,3d" "$sim_vcd"
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# remove the "opened file..." prompt from the log
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sed -i.orig -e "1,1d" "$sim_log"
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}
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assertConverts() {
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ac_file="$1"
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ac_tmpa="$SHUNIT_TMPDIR/ac-conv-tmpa.v"
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ac_tmpb="$SHUNIT_TMPDIR/ac-conv-tmpb.v"
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ac_tmpc="$SHUNIT_TMPDIR/ac-conv-tmpc.v"
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$SV2V "$ac_file" 2> /dev/null > "$ac_tmpa"
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assertTrue "1st conversion of $ac_file failed" $?
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$SV2V "$ac_tmpa" 2> /dev/null > "$ac_tmpb"
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assertTrue "2nd conversion of $ac_file failed" $?
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$SV2V "$ac_tmpb" 2> /dev/null > "$ac_tmpc"
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assertTrue "3rd conversion of $ac_file failed" $?
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diff "$ac_tmpb" "$ac_tmpc" > /dev/null
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assertTrue "conversion of $ac_file not stable after the second iteration" $?
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# using sed to remove quoted strings
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filtered=`sed -E 's/"([^"]|\")+"//g' "$ac_tmpa"`
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echo "$filtered" | grep "\$bits" > /dev/null
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assertFalse "conversion of $ac_file still contains \$bits" $?
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echo "$filtered" | grep "\]\[" > /dev/null
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assertFalse "conversion of $ac_file still contains multi-dim arrays" $?
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echo "$filtered" | egrep "\s(int\|bit\|logic\|byte\|struct\|enum\|longint\|shortint)\s"
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assertFalse "conversion of $ac_file still contains SV types" $?
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}
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simpleTest() {
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sv="$1"
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ve="$2"
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tb="$3"
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assertNotNull "SystemVerilog file not specified" $sv
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assertNotNull "Verilog file not specified" $ve
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assertNotNull "Testbench not specified" $tb
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# some tests don't have a separate testbench, instead having the top-level
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# module defined in both of the input files
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if [ ! -f "$tb" ]; then
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tb="$SCRIPT_DIR/empty.v"
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fi
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assertExists $sv
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assertExists $ve
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assertExists $tb
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assertConverts "$sv"
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assertConverts "$ve"
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assertConverts "$tb"
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# convert the SystemVerilog source file
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cv="$SHUNIT_TMPDIR/conv.v"
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$SV2V $sv 2> /dev/null > $cv
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assertTrue "conversion failed" $?
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assertExists $cv
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ref_vcd="$SHUNIT_TMPDIR/ref.vcd"
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gen_vcd="$SHUNIT_TMPDIR/gen.vcd"
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ref_log="$SHUNIT_TMPDIR/ref.log"
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gen_log="$SHUNIT_TMPDIR/gen.log"
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# simulate and compare the two files
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simulate "$ref_vcd" "$ref_log" top "$ve" "$tb"
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simulate "$gen_vcd" "$gen_log" top "$cv" "$tb"
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diff "$ref_vcd" "$gen_vcd" > /dev/null
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assertTrue "VCDs are different" $?
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output=`diff "$ref_log" "$gen_log"`
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assertTrue "Simulation outputs differ:\n$output" $?
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}
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runTest() {
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test="$1"
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simpleTest "${test}.sv" "${test}.v" "${test}_tb.v"
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}
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suite() {
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for test in `ls *.sv | sed -e "s_\.sv\\\$__"`; do
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@ -118,5 +9,6 @@ suite() {
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done
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}
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. shunit2
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source "$SCRIPT_DIR/functions.sh"
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. shunit2
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@ -0,0 +1,9 @@
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module top
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import pkg::*;
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#(parameter width = width_calc(2))
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(input [width-1:0] i, output [width-1:0] o);
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assign o = i + 1'b1;
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initial begin
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$display(width);
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end
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endmodule
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@ -0,0 +1,6 @@
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package pkg;
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function automatic integer width_calc;
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input integer a;
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return a+3;
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endfunction
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endpackage
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@ -0,0 +1,9 @@
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module top;
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parameter width = 5;
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input [width-1:0] i;
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output [width-1:0] o;
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assign o = i + 1'b1;
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initial begin
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$display(width);
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end
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endmodule
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@ -0,0 +1,15 @@
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#!/bin/bash
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test_main() {
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cv="$SHUNIT_TMPDIR/conv.v"
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convert "$cv" package.svh module.sv
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simulateAndCompare "reference.v" "$cv" "$SCRIPT_DIR/empty.v"
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}
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suite() {
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suite_addTest "test_main"
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}
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source ../lib/functions.sh
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. shunit2
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