fixed dimension shorthand diretion and relevant tests

src/Language/SystemVerilog/Parser/Parse.y

@@ -802,7 +802,7 @@ DimensionsNonEmpty :: { [Range] }
   | DimensionsNonEmpty Dimension { $1 ++ [$2] }
 Dimension :: { Range }
   : Range        { $1 }
-  | "[" Expr "]" { (simplify $  BinOp Sub $2 (Number "1"), Number "0") }
+  | "[" Expr "]" { (Number "0", BinOp Sub $2 (Number "1")) }
 
 DeclAsgns :: { [(Identifier, Expr, [Range])] }
   : DeclAsgn               { [$1] }

src/Language/SystemVerilog/Parser/ParseDecl.hs

@@ -357,7 +357,7 @@ takeRanges (token : tokens) =
         _                       -> ([]            , token : tokens)
     where
         (rs, rest) = takeRanges tokens
-        asRange s = (simplify $ BinOp Sub s (Number "1"), Number "0")
+        asRange s = (Number "0", BinOp Sub s (Number "1"))
 
 -- Matching DTAsgnNBlk here allows tripLookahead to work both for standard
 -- declarations and in `parseDTsAsDeclOrAsgn`, where we're checking for an

test/basic/multipack_port.sv

@@ -14,3 +14,20 @@ module foo(clock, data);
         data[0][0] = ~data[0][0];
     end
 endmodule
+
+module top;
+  logic [10:0] data [5];
+    reg clock;
+    foo f(clock, data);
+
+    initial begin
+        clock = 1;
+        forever #1 clock = ~clock;
+    end
+
+    initial begin : foo
+        $monitor("%d %b%b%b%b%b", $time, data[0], data[1], data[2], data[3], data[4]);
+        #100;
+        $finish();
+    end
+endmodule

test/basic/multipack_port.v

@@ -1,12 +1,33 @@
 module foo(clock, data);
     input clock;
     output reg [54:0] data;
-    initial data[0] = 0;
+    initial data[11*4] = 0;
     always @(clock) begin : block_name
-        integer i;
-        for (i = 53; i >= 0; i = i - 1) begin
-            data[i+1] = data[i];
+        integer i, j;
+        for (i = 4; i >= 0; i--) begin
+            for (j = 9; j >= 0; j--) begin
+                data[11*(4-i) + j + 1] = data[11*(4-i) + j];
+            end
+            if (i != 0)
+                data[11*(4-i) + 0] = data[11*(4-(i-1)) + 10];
         end
-        data[0] = ~data[0];
+        data[11*4] = ~data[11*4];
+    end
+endmodule
+
+module top;
+    wire [54:0] data;
+    reg clock;
+    foo f(clock, data);
+
+    initial begin
+        clock = 1;
+        forever #1 clock = ~clock;
+    end
+
+    initial begin : foo
+        $monitor("%d %b", $time, data);
+        #100;
+        $finish();
     end
 endmodule

test/basic/multipack_port_tb.v

@@ -1,16 +0,0 @@
-module top;
-    wire [0:54] data;
-    reg clock;
-    foo f(clock, data);
-
-    initial begin
-        clock = 1;
-        forever #1 clock = ~clock;
-    end
-
-    initial begin : foo
-        $monitor("%d %b", $time, data);
-        #100;
-        $finish();
-    end
-endmodule

test/basic/unpacked_localparam.v

@@ -2,7 +2,7 @@ module top;
     localparam [31:0] init_val = {8'd0, 8'd8, 8'd10, 8'd200};
     initial begin : foo
         integer i, j;
-        for (i = 0; i < 4; i += 1) begin
+        for (i = 3; i >= 0; i -= 1) begin
             $display(init_val[8*i+:8]);
             for (j = 0; j < 8; j += 1) begin
                 $display(init_val[8*i+j]);