mirror of https://github.com/zachjs/sv2v.git
support and conversion for foreach
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Zachary Snow
parent
7f701cd112
commit
77b9d2f085
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@ -17,6 +17,7 @@ import qualified Convert.DimensionQuery
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import qualified Convert.EmptyArgs
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import qualified Convert.Enum
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import qualified Convert.ForDecl
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import qualified Convert.Foreach
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import qualified Convert.FuncRet
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import qualified Convert.Interface
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import qualified Convert.IntTypes
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@ -69,6 +70,7 @@ phases excludes =
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, Convert.Enum.convert
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, Convert.NestPI.convert
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, Convert.Return.convert
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, Convert.Foreach.convert
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, selectExclude (Job.Interface, Convert.Interface.convert)
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, selectExclude (Job.Always , Convert.AlwaysKW.convert)
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, selectExclude (Job.Succinct , Convert.RemoveComments.convert)
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@ -0,0 +1,38 @@
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{- sv2v
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- Author: Zachary Snow <zach@zachjs.com>
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-
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- Conversion for `foreach` loops.
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-
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- We simply convert these loops to a series of loops, with the bounds and
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- direction provided by the array dimension query system functions. Omitted
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- indices are skipped.
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-}
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module Convert.Foreach (convert) where
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import Convert.Traverse
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import Language.SystemVerilog.AST
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convert :: [AST] -> [AST]
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convert =
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map $ traverseDescriptions $ traverseModuleItems $
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traverseStmts convertStmt
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convertStmt :: Stmt -> Stmt
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convertStmt (Foreach x idxs stmt) =
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(foldl (.) id $ map toLoop $ zip [1..] idxs) stmt
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where
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toLoop :: (Int, Maybe Identifier) -> (Stmt -> Stmt)
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toLoop (_, Nothing) = id
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toLoop (d, Just i) =
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For [Left idxDecl] (Just cmp) [incr]
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where
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queryFn f = DimFn f (Right $ Ident x) (Number $ show d)
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idxDecl = Variable Local (IntegerAtom TInteger Unspecified) i []
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$ Just $ queryFn FnLeft
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cmp =
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Mux (BinOp Eq (queryFn FnIncrement) (Number "1"))
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(BinOp Ge (Ident i) (queryFn FnRight))
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(BinOp Le (Ident i) (queryFn FnRight))
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incr = (LHSIdent i, AsgnOp Sub, queryFn FnIncrement)
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convertStmt other = other
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@ -235,6 +235,7 @@ traverseSinglyNestedStmtsM fullMapper = cs
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cs (RepeatL e stmt) = fullMapper stmt >>= return . RepeatL e
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cs (DoWhile e stmt) = fullMapper stmt >>= return . DoWhile e
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cs (Forever stmt) = fullMapper stmt >>= return . Forever
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cs (Foreach x vars stmt) = fullMapper stmt >>= return . Foreach x vars
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cs (If u e s1 s2) = do
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s1' <- fullMapper s1
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s2' <- fullMapper s2
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@ -682,6 +683,7 @@ traverseStmtExprsM exprMapper = flatStmtMapper
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flatStmtMapper (DoWhile e stmt) =
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exprMapper e >>= \e' -> return $ DoWhile e' stmt
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flatStmtMapper (Forever stmt) = return $ Forever stmt
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flatStmtMapper (Foreach x vars stmt) = return $ Foreach x vars stmt
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flatStmtMapper (If u cc s1 s2) =
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exprMapper cc >>= \cc' -> return $ If u cc' s1 s2
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flatStmtMapper (Timing event stmt) = return $ Timing event stmt
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@ -162,6 +162,8 @@ readNumber n =
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-- basic expression simplfication utility to help us generate nicer code in the
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-- common case of ranges like `[FOO-1:0]`
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simplify :: Expr -> Expr
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simplify (UniOp LogNot (Number "1")) = Number "0"
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simplify (UniOp LogNot (Number "0")) = Number "1"
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simplify (Repeat (Number "0") _) = Concat []
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simplify (Concat [expr]) = expr
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simplify (Concat exprs) =
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@ -170,23 +172,17 @@ simplify (orig @ (Call Nothing "$clog2" (Args [Just (Number n)] []))) =
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case readNumber n of
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Nothing -> orig
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Just x -> Number $ show $ clog2 x
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simplify (Mux (Number "0") e _) = e
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simplify (Mux (BinOp Ge c1 c2) e1 e2) =
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case (c1', c2') of
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(Number a, Number b) ->
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case (readNumber a, readNumber b) of
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(Just x, Just y) ->
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if x >= y
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then e1
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else e2
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_ -> nochange
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_ -> nochange
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simplify (Mux cc e1 e2) =
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case cc' of
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Number "1" -> e1'
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Number "0" -> e2'
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_ -> Mux cc' e1' e2'
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where
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c1' = simplify c1
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c2' = simplify c2
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cc' = simplify cc
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e1' = simplify e1
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e2' = simplify e2
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nochange = Mux (BinOp Ge c1' c2') e1' e2'
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simplify (Range e NonIndexed r) = Range e NonIndexed r
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simplify (Range e _ (i, Number "0")) = Bit e i
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simplify (BinOp Sub (Number n1) (BinOp Sub (Number n2) e)) =
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simplify $ BinOp Add (BinOp Sub (Number n1) (Number n2)) e
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simplify (BinOp Sub (Number n1) (BinOp Sub e (Number n2))) =
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@ -211,21 +207,30 @@ simplify (BinOp op e1 e2) =
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(Add, BinOp Sub e (Number "1"), Number "1") -> e
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(Add, e, BinOp Sub (Number "0") (Number "1")) -> BinOp Sub e (Number "1")
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(_ , Number a, Number b) ->
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case (op, readNumber a, readNumber b) of
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case (op, readNumber a :: Maybe Int, readNumber b :: Maybe Int) of
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(Add, Just x, Just y) -> Number $ show (x + y)
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(Sub, Just x, Just y) -> Number $ show (x - y)
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(Mul, Just x, Just y) -> Number $ show (x * y)
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(Div, Just _, Just 0) -> Number "x"
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(Div, Just x, Just y) -> Number $ show (x `quot` y)
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(Eq , Just x, Just y) -> bool $ x == y
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(Ne , Just x, Just y) -> bool $ x /= y
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(Gt , Just x, Just y) -> bool $ x > y
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(Ge , Just x, Just y) -> bool $ x >= y
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(Lt , Just x, Just y) -> bool $ x < y
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(Le , Just x, Just y) -> bool $ x <= y
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_ -> BinOp op e1' e2'
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(Add, BinOp Add e (Number a), Number b) ->
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case (readNumber a, readNumber b) of
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(Just x, Just y) -> BinOp Add e $ Number $ show (x + y)
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_ -> BinOp op e1' e2'
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(Sub, e, Number "-1") -> BinOp Add e (Number "1")
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_ -> BinOp op e1' e2'
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where
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e1' = simplify e1
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e2' = simplify e2
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bool True = Number "1"
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bool False = Number "0"
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simplify other = other
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rangeSize :: Range -> Expr
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@ -258,7 +263,10 @@ sizedExpr x s (Number n) =
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++ " doesn't have size " ++ show size
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else Number res
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where
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Number size = simplify s
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size =
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case simplify s of
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Number v -> v
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other -> error $ "could not simplify sizedExpr: " ++ show other
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unticked = case n of
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'\'' : rest -> rest
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rest -> rest
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@ -43,6 +43,7 @@ data Stmt
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| RepeatL Expr Stmt
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| DoWhile Expr Stmt
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| Forever Stmt
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| Foreach Identifier [Maybe Identifier] Stmt
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| If (Maybe UniquePriority) Expr Stmt Stmt
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| Timing Timing Stmt
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| Return Expr
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@ -86,6 +87,7 @@ instance Show Stmt where
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show (RepeatL e s) = printf "repeat (%s) %s" (show e) (show s)
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show (DoWhile e s) = printf "do %s while (%s);" (show s) (show e)
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show (Forever s ) = printf "forever %s" (show s)
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show (Foreach x i s) = printf "foreach (%s [ %s ]) %s" x (commas $ map (maybe "" id) i) (show s)
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show (If u a b Null) = printf "%sif (%s) %s" (maybe "" showPad u) (show a) (show b)
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show (If u a b c ) = printf "%sif (%s) %s\nelse %s" (maybe "" showPad u) (show a) (show b) (show c)
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show (Return e ) = printf "return %s;" (show e)
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@ -95,7 +95,10 @@ nullRange :: Type -> ([Range] -> Type)
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nullRange t [] = t
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nullRange t [(Number "0", Number "0")] = t
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nullRange (IntegerAtom TInteger sg) rs =
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-- integer arrays are allowed in SystemVerilog but not in Verilor
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-- integer arrays are allowed in SystemVerilog but not in Verilog
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IntegerVector TBit sg (rs ++ [(Number "31", Number "0")])
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nullRange (IntegerAtom TInt sg) rs =
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-- int arrays are allowed in SystemVerilog but not in Verilog
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IntegerVector TBit sg (rs ++ [(Number "31", Number "0")])
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nullRange t rs =
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error $ "non-vector type " ++ show t ++
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@ -884,6 +884,7 @@ StmtNonAsgn :: { Stmt }
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| "repeat" "(" Expr ")" Stmt { RepeatL $3 $5 }
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| "do" Stmt "while" "(" Expr ")" ";" { DoWhile $5 $2 }
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| "forever" Stmt { Forever $2 }
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| "foreach" "(" Identifier IdxVars ")" Stmt { Foreach $3 $4 $6 }
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| "->" Identifier ";" { Trigger $2 }
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| AttributeInstance Stmt { StmtAttr $1 $2 }
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| ProceduralAssertionStatement { Assertion $1 }
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@ -905,6 +906,12 @@ ForStepAssignment :: { (LHS, AsgnOp, Expr) }
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| IncOrDecOperator LHS { ($2, AsgnOp $1, Number "1") }
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| LHS IncOrDecOperator { ($1, AsgnOp $2, Number "1") }
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IdxVars :: { [Maybe Identifier] }
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: "[" IdxVarsInside "]" { $2 }
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IdxVarsInside :: { [Maybe Identifier] }
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: opt(Identifier) { [$1] }
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| opt(Identifier) "," IdxVarsInside { $1 : $3 }
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DeclsAndStmts :: { ([Decl], [Stmt]) }
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: DeclOrStmt DeclsAndStmts { combineDeclsAndStmts $1 $2 }
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| StmtNonAsgn Stmts { ([], $1 : $2) }
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@ -62,6 +62,7 @@ executable sv2v
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Convert.EmptyArgs
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Convert.Enum
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Convert.ForDecl
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Convert.Foreach
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Convert.FuncRet
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Convert.Interface
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Convert.IntTypes
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@ -0,0 +1,18 @@
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module top;
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logic [1:0] foo [4] = {2'b10,2'b01,2'b11,2'b00};
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initial
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foreach (foo [ x ])
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$display(x, foo[x]);
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// from the SystemVerilog-2017 specification
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int A [2][3][4];
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bit [3:0][2:1] B [5:1][4];
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initial begin
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A = 0;
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B = 0;
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foreach( A [ i, j, k ] )
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$display(i, j, k);
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foreach( B [ q, r, , s ] )
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$display(q, r, s);
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end
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endmodule
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@ -0,0 +1,29 @@
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module top;
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wire [7:0] foo = {2'b10,2'b01,2'b11,2'b00};
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initial begin : f
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integer x;
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for (x = 0; x <= 3; x = x + 1)
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$display(x, foo[6 - 2*x+:2]);
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end
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reg [32*2*3*4 - 1:0] A;
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reg [5*4*4*2 + 32: 1 + 32] B;
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initial begin
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A = 0;
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B = 0;
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begin : g
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integer i, j, k;
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for (i = 0; i <= 1; i = i + 1)
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for (j = 0; j <= 2; j = j + 1)
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for (k = 0; k <= 3; k = k + 1)
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$display(i, j, k);
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end
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begin : h
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integer q, r, s;
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for (q = 5; q >= 1; q = q - 1)
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for (r = 0; r <= 3; r = r + 1)
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for (s = 2; s >= 1; s = s - 1)
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$display(q, r, s);
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end
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end
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endmodule
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@ -113,8 +113,8 @@ simulateAndCompare() {
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# simulate and compare the two files
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simulate "$ref_vcd" "$ref_log" top "$ve" "$tb"
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simulate "$gen_vcd" "$gen_log" top "$cv" "$tb"
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diff "$ref_vcd" "$gen_vcd" > /dev/null
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assertTrue "VCDs are different" $?
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output=`diff "$ref_vcd" "$gen_vcd"`
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assertTrue "VCDs are different:\n$output" $?
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output=`diff "$ref_log" "$gen_log"`
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assertTrue "Simulation outputs differ:\n$output" $?
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}
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