refactor

README.md

@@ -102,7 +102,7 @@ Preprocessing:
 Conversion:
      --pass-through         Dump input without converting
   -E --exclude=CONV         Exclude a particular conversion (Always, Assert,
-                            Interface, Logic, or UnbasedUnsized)
+                            Interface, Logic, SeverityTasks, or UnbasedUnsized)
   -v --verbose              Retain certain conversion artifacts
   -w --write=MODE/FILE/DIR  How to write output; default is 'stdout'; use
                             'adjacent' to create a .v file next to each input;

src/Convert.hs

@@ -51,7 +51,7 @@ import qualified Convert.StringParam
 import qualified Convert.StringType
 import qualified Convert.Struct
 import qualified Convert.StructConst
-import qualified Convert.SystemTasks
+import qualified Convert.SeverityTasks
 import qualified Convert.TFBlock
 import qualified Convert.Typedef
 import qualified Convert.TypeOf
@@ -122,7 +122,7 @@ initialPhases tops selectExclude =
     , Convert.Interface.disambiguate
     , Convert.Package.convert
     , Convert.StructConst.convert
-    , Convert.SystemTasks.convert
+    , selectExclude Job.SeverityTasks Convert.SeverityTasks.convert
     , Convert.PortDecl.convert
     , Convert.ParamNoDefault.convert tops
     , Convert.ResolveBindings.convert

src/Convert/SeverityTasks.hs

@@ -1,10 +1,17 @@
 {- sv2v
-- Author: Ethan Sifferman <ethan@sifferman.dev>
--
-- Conversion of SystemVerilog System Tasks to Verilog.
--}
+ - Author: Ethan Sifferman <ethan@sifferman.dev>
+ -
+ - Conversion of standard and elaboration severity tasks `$info`, `$warning`,
+ - `$error`, and `$fatal` (20.10 and 20.11).
+ -
+ -  * Severity task messages are converted into `$display` tasks.
+ -  * Standard `$fatal` tasks run `$finish` directly after running `$display`.
+ -  * Elaboration `$fatal` tasks set `_sv2v_elaboration_fatal` to a
+ -    non-negative value, causing the simulation to exit once all elaboration
+ -    severity task messages have been printed.
+ -}
 
-module Convert.SystemTasks (convert) where
+module Convert.SeverityTasks (convert) where
 
 import Convert.Traverse
 import Language.SystemVerilog.AST

src/Job.hs

@@ -27,6 +27,7 @@ data Exclude
     | Assert
     | Interface
     | Logic
+    | SeverityTasks
     | Succinct
     | UnbasedUnsized
     deriving (Typeable, Data, Eq)
@@ -83,7 +84,7 @@ defaultJob = Job
         &= groupname "Conversion"
     , exclude = nam_ "exclude" &= name "E" &= typ "CONV"
         &= help ("Exclude a particular conversion (Always, Assert, Interface,"
-            ++ " Logic, or UnbasedUnsized)")
+            ++ " Logic, SeverityTasks, or UnbasedUnsized)")
     , verbose = nam "verbose" &= help "Retain certain conversion artifacts"
     , write = Stdout &= ignore -- parsed from the flexible flag below
     , writeRaw = "s" &= name "write" &= name "w" &= explicit

sv2v.cabal

@@ -104,7 +104,7 @@ executable sv2v
     Convert.StringType
     Convert.Struct
     Convert.StructConst
-    Convert.SystemTasks
+    Convert.SeverityTasks
     Convert.TFBlock
     Convert.Traverse
     Convert.Typedef