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support bare delay controls with real number delays

This commit is contained in:
Zachary Snow 2021-08-17 09:53:28 -06:00
parent 69874edc80
commit 7325bd7976
3 changed files with 12 additions and 0 deletions
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1
CHANGELOG.md
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@ -16,6 +16,7 @@
* Tolerate escaped vendor block comments in macro bodies * Tolerate escaped vendor block comments in macro bodies
* Support deferred immediate assertion statements * Support deferred immediate assertion statements
* Apply implicit port directions to tasks and functions * Apply implicit port directions to tasks and functions
* Support bare delay controls with real number delays
## v0.0.8 ## v0.0.8

1
src/Language/SystemVerilog/Parser/Parse.y
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@ -1162,6 +1162,7 @@ DelayOrEvent :: { Timing }
| EventControl { Event $1 } | EventControl { Event $1 }
DelayControl :: { Expr } DelayControl :: { Expr }
: "#" Number { Number $2 } : "#" Number { Number $2 }
| "#" Real { Real $2 }
| "#" Time { Time $2 } | "#" Time { Time $2 }
| "#" "(" Expr ")" { $3 } | "#" "(" Expr ")" { $3 }
| "#" "(" Expr ":" Expr ":" Expr ")" { MinTypMax $3 $5 $7 } | "#" "(" Expr ":" Expr ":" Expr ")" { MinTypMax $3 $5 $7 }

10
test/basic/delay_real.sv Normal file
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@ -0,0 +1,10 @@
module top;
reg x, y;
initial begin
$monitor($time, x, y);
#1 x = 0;
#1 x = 1;
#0.75 y = 0;
#0.75 y = 1;
end
endmodule