mirror of https://github.com/zachjs/sv2v.git
pursue a different approach and update test case
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@ -33,7 +33,7 @@ import Language.SystemVerilog.Parser.Tokens
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%tokentype { Token }
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%tokentype { Token }
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%error { parseErrorTok }
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%error { parseErrorTok }
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%expect 4
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%expect 0
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%token
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%token
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@ -947,17 +947,9 @@ ImportOrExport :: { [PackageItem] }
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: "import" PackageImportItems ";" { map (uncurry Import) $2 }
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: "import" PackageImportItems ";" { map (uncurry Import) $2 }
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| "export" PackageImportItems ";" { map (uncurry Export) $2 }
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| "export" PackageImportItems ";" { map (uncurry Export) $2 }
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| "export" "*" "::" "*" ";" { [Export "" ""] }
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| "export" "*" "::" "*" ";" { [Export "" ""] }
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BlockItemDecls :: { [Decl] }
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: {- empty -} { [] }
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| ";" BlockItemDecls { $2 }
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| BlockItemDecl BlockItemDecls { $1 ++ $2 }
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BlockItemDecl :: { [Decl] }
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: DataDecl { $1 }
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DataDecl :: { [Decl] }
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: Typedef { [$1] }
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TaskOrFunction :: { PackageItem }
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TaskOrFunction :: { PackageItem }
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: "function" Lifetime FuncRetAndName TFItems BlockItemDecls DeclsAndStmts endfunction StrTag {% checkTag (snd $3) $8 $ Function $2 (fst $3) (snd $3) (map makeInput $4 ++ $5 ++ fst $6) (snd $6) }
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: "function" Lifetime FuncRetAndName TFItems DeclsAndStmts endfunction StrTag {% checkTag (snd $3) $7 $ Function $2 (fst $3) (snd $3) (map makeInput $4 ++ fst $5) (snd $5) }
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| "task" Lifetime Identifier TFItems BlockItemDecls DeclsAndStmts endtask StrTag {% checkTag $3 $8 $ Task $2 $3 ($4 ++ $5 ++ fst $6) (snd $6) }
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| "task" Lifetime Identifier TFItems DeclsAndStmts endtask StrTag {% checkTag $3 $7 $ Task $2 $3 ($4 ++ fst $5) (snd $5) }
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Typedef :: { Decl }
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Typedef :: { Decl }
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: "typedef" Type Identifier ";" { ParamType Localparam $3 $2 }
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: "typedef" Type Identifier ";" { ParamType Localparam $3 $2 }
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| "typedef" Type Identifier DimensionsNonEmpty ";" { ParamType Localparam $3 (UnpackedType $2 $4) }
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| "typedef" Type Identifier DimensionsNonEmpty ";" { ParamType Localparam $3 (UnpackedType $2 $4) }
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@ -1234,6 +1226,7 @@ DeclsAndStmts :: { ([Decl], [Stmt]) }
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DeclOrStmt :: { ([Decl], [Stmt]) }
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DeclOrStmt :: { ([Decl], [Stmt]) }
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: DeclTokens(";") { parseDTsAsDeclOrStmt $1 }
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: DeclTokens(";") { parseDTsAsDeclOrStmt $1 }
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| ParameterDecl(";") { ($1, []) }
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| ParameterDecl(";") { ($1, []) }
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| Typedef { ([$1], []) }
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ParameterDecl(delim) :: { [Decl] }
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ParameterDecl(delim) :: { [Decl] }
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: ParameterDeclKW DeclAsgns delim { makeParamDecls $1 (Implicit Unspecified []) $2 }
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: ParameterDeclKW DeclAsgns delim { makeParamDecls $1 (Implicit Unspecified []) $2 }
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@ -1,12 +1,17 @@
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module top;
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module top;
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task t;
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task t;
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typedef bit u;
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typedef byte u;
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$display("t = %d", u'(0));
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$display("t %b", u'('1));
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endtask
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endtask
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function f;
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function integer f;
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typedef bit u;
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input reg signed i;
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return u'(1);
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typedef shortint v;
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$display("i %b", v'(i));
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return $bits(v);
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endfunction
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endfunction
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initial t();
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initial begin
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initial $display("f = %d", f());
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t();
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$display("f %b", f(0));
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$display("f %b", f(1));
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end
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endmodule
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endmodule
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@ -1,11 +1,19 @@
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module top;
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module top;
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task t;
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task t;
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$display("t = %d", 1'd0);
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$display("t %b", 8'hFF);
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endtask
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endtask
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function f;
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function integer f;
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input reg _sv2v_unused;
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input reg signed i;
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f = 1'd1;
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reg [15:0] j;
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endfunction
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begin
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initial t;
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j = i;
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initial $display("f = %d", f(0));
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$display("i %b", j);
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f = 16;
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end
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endfunction
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initial begin
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t;
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$display("f %b", f(0));
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$display("f %b", f(1));
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end
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endmodule
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endmodule
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