fix missing top reference renames in param type instantiation

- renaming applies to nodes within generate blocks
- renaming applies to LHSs

src/Convert/ParamType.hs

@@ -149,8 +149,10 @@ convert files =
             where
                 Part attrs extern kw ml m p items = part
                 m' = moduleInstanceName m typeMap
-                items' = map (traverseExprs rewriteExpr) $
+                items' = map rewriteModuleItem items
-                    map (traverseDecls rewriteDecl) items
+                rewriteModuleItem = traverseDecls rewriteDecl .
+                    traverseNestedModuleItems
+                        (traverseExprs rewriteExpr . traverseLHSs rewriteLHS)
                 rewriteDecl :: Decl -> Decl
                 rewriteDecl (ParamType Parameter x _) =
                     ParamType Localparam x (fst $ typeMap Map.! x)
@@ -165,6 +167,14 @@ convert files =
                 rewriteExpr other =
                     traverseExprTypes rewriteType $
                     traverseSinglyNestedExprs rewriteExpr other
+                rewriteLHS :: LHS -> LHS
+                rewriteLHS (orig @ (LHSDot (LHSIdent x) y)) =
+                    if x == m
+                        then LHSDot (LHSIdent m') y
+                        else orig
+                rewriteLHS other =
+                    traverseLHSExprs rewriteExpr $
+                    traverseSinglyNestedLHSs rewriteLHS other
                 rewriteType :: Type -> Type
                 rewriteType =
                     traverseNestedTypes $ traverseTypeExprs rewriteExpr

test/basic/paramtype_hier.sv

@@ -1,8 +1,15 @@
-module Module;
+module Module #(
-    parameter int S;
+    parameter int S,
-    parameter type T;
+    parameter type T
-    T x = '1;
+);
-    initial $display("Module %0d: %b, %0d", S, Module.x, $bits(T));
+    T x;
+    if (S) begin : a
+        if (S) begin : b
+            assign Module.x = '1;
+            logic [$bits(Module.x):0] y = 'z;
+        end
+    end
+    initial $display("Module %0d: %b %0d %b %0d", S, Module.x, $bits(T), Module.a.b.y, $bits(Module.a.b.y));
 endmodule
 
 module top;

test/basic/paramtype_hier.v

@@ -1,8 +1,16 @@
 module Module;
     parameter S = 0;
     parameter T = 0;
-    wire [T-1:0] x = 1'sb1;
+    wire [T-1:0] x;
-    initial $display("Module %0d: %b, %0d", S, Module.x, T);
+    generate
+        if (S) begin : a
+            if (S) begin : b
+                assign Module.x = 1'sb1;
+                wire [T:0] y = 1'sbz;
+            end
+        end
+    endgenerate
+    initial $display("Module %0d: %b %0d %b %0d", S, Module.x, T, Module.a.b.y, T + 1);
 endmodule
 
 module top;