mirror of https://github.com/zachjs/sv2v.git
logic conversion makes continuous assignments procedural where necessary
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@ -19,7 +19,7 @@ import qualified Data.Set as Set
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import Convert.Traverse
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import Language.SystemVerilog.AST
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type RegIdents = Set.Set String
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type Idents = Set.Set Identifier
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convert :: AST -> AST
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convert = traverseDescriptions convertDescription
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@ -38,6 +38,12 @@ convertDescription orig =
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conversion = traverseDecls convertDecl . convertModuleItem
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idents = execWriter (collectModuleItemsM regIdents orig)
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convertModuleItem :: ModuleItem -> ModuleItem
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convertModuleItem (Assign Nothing lhs expr) =
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if Set.null $ Set.intersection usedIdents idents
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then Assign Nothing lhs expr
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else AlwaysC AlwaysComb $ AsgnBlk AsgnOpEq lhs expr
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where
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usedIdents = execWriter $ collectNestedLHSsM lhsIdents lhs
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convertModuleItem (MIDecl (Variable dir (IntegerVector TLogic sg mr) ident a me)) =
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MIDecl $ Variable dir (t mr) ident a me
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where
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@ -55,17 +61,18 @@ convertDescription orig =
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Variable d (IntegerVector TReg sg rs) x a me
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convertDecl other = other
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regIdents :: ModuleItem -> Writer RegIdents ()
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regIdents :: ModuleItem -> Writer Idents ()
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regIdents (AlwaysC _ stmt) =
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collectNestedStmtsM (collectStmtLHSsM (collectNestedLHSsM idents)) $
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collectNestedStmtsM (collectStmtLHSsM (collectNestedLHSsM lhsIdents)) $
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traverseNestedStmts removeTimings stmt
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where
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idents :: LHS -> Writer RegIdents ()
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idents (LHSIdent vx ) = tell $ Set.singleton vx
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idents _ = return () -- the collector recurses for us
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removeTimings :: Stmt -> Stmt
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removeTimings (Timing _ s) = s
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removeTimings other = other
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regIdents (Initial stmt) =
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regIdents $ AlwaysC Always stmt
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regIdents _ = return ()
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lhsIdents :: LHS -> Writer Idents ()
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lhsIdents (LHSIdent vx ) = tell $ Set.singleton vx
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lhsIdents _ = return () -- the collector recurses for us
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