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minor readme tweaks
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README.md
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README.md
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## Supported Features
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sv2v supports most synthesizable SystemVerilog features. Current notable
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exceptions include `defparam` on interface instances and certain synthesizable
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usages of parameterized classes. Assertions are also supported, but are simply
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dropped during conversion.
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exceptions include `defparam` on interface instances, certain synthesizable
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usages of parameterized classes, and the `bind` keyword. Assertions are also
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supported, but are simply dropped during conversion.
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If you find a bug or have a feature request, please create an issue. Preference
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will be given to issues which include examples or test cases.
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If you find a bug or have a feature request, please [create an issue].
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Preference will be given to issues which include examples or test cases.
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[create an issue]: https://github.com/zachjs/sv2v/issues/new
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## SystemVerilog Front End
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