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support module "list of param assignments" shorthand

This commit is contained in:
Zachary Snow 2019-09-17 19:48:08 -04:00
parent bdafb60dec
commit 512d4b1a7f
3 changed files with 26 additions and 2 deletions
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10
src/Language/SystemVerilog/Parser/Parse.y
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@ -528,8 +528,14 @@ Params :: { [ModuleItem] }
: {- empty -} { [] }
| "#" "(" ParamsFollow { map (MIPackageItem . Decl) $3 }
ParamsFollow :: { [Decl] }
: ParameterDecl(")") { $1 }
| ParameterDecl(",") ParamsFollow { $1 ++ $2 }
: ParamAsgn ")" { [$1] }
| ParamAsgn "," ParamsFollow { $1 : $3 }
| ParamsDecl { $1 }
ParamsDecl :: { [Decl] }
: ParameterDecl(")") { $1 }
| ParameterDecl(",") ParamsDecl { $1 ++ $2 }
ParamAsgn :: { Decl }
: Identifier "=" Expr { Param Parameter (Implicit Unspecified []) $1 $3 }
PortDecls :: { ([Identifier], [ModuleItem]) }
: "(" DeclTokens(")") { parseDTsAsPortDecls $2 }

9
test/basic/param_shorthand.sv Normal file
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@ -0,0 +1,9 @@
module top #(FOO = 10);
initial $display(FOO);
endmodule
module top2 #(FOO = 10, BAR = 11);
initial $display(FOO, BAR);
endmodule
module top3 #(FOO = 10, BAR = 11, parameter BAZ = 12);
initial $display(FOO, BAR, BAZ);
endmodule

9
test/basic/param_shorthand.v Normal file
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@ -0,0 +1,9 @@
module top #(parameter FOO = 10);
initial $display(FOO);
endmodule
module top2 #(parameter FOO = 10, parameter BAR = 11);
initial $display(FOO, BAR);
endmodule
module top3 #(parameter FOO = 10, parameter BAR = 11, parameter BAZ = 12);
initial $display(FOO, BAR, BAZ);
endmodule