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module item attrs aren't mapped onto trace statements

This commit is contained in:
Zachary Snow 2021-02-17 13:35:10 -05:00
parent 0d095e6afb
commit 4bfcfe4b28
1 changed files with 5 additions and 1 deletions
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6
src/Language/SystemVerilog/Parser/Parse.y
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@ -689,7 +689,7 @@ NonGenerateModuleItem :: { [ModuleItem] }
| NonDeclPackageItem { map MIPackageItem $1 }
| NInputGateKW NInputGates ";" { map (\(a, b, c, d) -> NInputGate $1 a b c d) $2 }
| NOutputGateKW NOutputGates ";" { map (\(a, b, c, d) -> NOutputGate $1 a b c d) $2 }
| AttributeInstance ModuleItem { map (MIAttr $1) $2 }
| AttributeInstance ModuleItem { map (addMIAttr $1) $2 }
| AssertionItem { [AssertionItem $1] }
AssignOption :: { AssignOption }
@ -1469,4 +1469,8 @@ rangeAsExpr :: ExprOrRange -> Expr
rangeAsExpr (Left e) = e
rangeAsExpr (Right r) = Range Nil NonIndexed r
addMIAttr :: Attr -> ModuleItem -> ModuleItem
addMIAttr _ (item @ (MIPackageItem (Decl CommentDecl{}))) = item
addMIAttr attr item = MIAttr attr item
}