zero-pad sized integrals smaller than 32 bits

2020-07-23 22:46:19 -06:00 · 2020-07-23 22:46:19 -06:00 · 39519dd439
parent f0a5a47371
commit 39519dd439
1 changed files with 1 additions and 1 deletions
--- a/src/Language/SystemVerilog/AST/Number.hs
+++ b/src/Language/SystemVerilog/AST/Number.hs
@ -237,7 +237,7 @@ showBasedDigits base size values kinds =
        padList '0' sizeDigits digits
    else if leadingXZ && size < 0 then
        removeExtraPadding digits
-    else if leadingXZ then
+    else if leadingXZ || (32 > size && size > 0) then
        padList '0' sizeDigits digits
    else
        digits