more proper support for always constructs and event_controls

Convert.hs

@@ -72,12 +72,13 @@ getStmtLHSs (BlockingAssignment    lhs _) = [lhs]
 getStmtLHSs (NonBlockingAssignment lhs _) = [lhs]
 getStmtLHSs (For _ _ _ stmt) = getStmtLHSs stmt
 getStmtLHSs (If _ s1 s2) = (getStmtLHSs s1) ++ (getStmtLHSs s2)
+getStmtLHSs (Timing _ s) = getStmtLHSs s
 getStmtLHSs (Null) = []
 
 getTypeInfoModuleItem :: ModulePorts -> ModuleItem -> TypeInfo
 getTypeInfoModuleItem _ (Assign lhs _) =
     Map.fromList $ zip (getLHSIdentifiers lhs) (repeat onlyAsWire)
-getTypeInfoModuleItem _ (Always _ stmt) =
+getTypeInfoModuleItem _ (AlwaysC _ stmt) =
     Map.fromList $ zip idents (repeat onlyAsReg)
     where
         lhss = getStmtLHSs stmt

Language/SystemVerilog/AST.hs

@@ -15,6 +15,7 @@ module Language.SystemVerilog.AST
   , Localparam (..)
   , IntegerV   (..)
   , GenItem    (..)
+  , AlwaysKW (..)
   , PortBinding
   , Case
   , Range
@@ -82,7 +83,7 @@ data ModuleItem
   | MIIntegerV   IntegerV
   | PortDecl   Direction (Maybe Range) Identifier
   | LocalNet   Type Identifier RangesOrAssignment
-  | Always     (Maybe Sense) Stmt
+  | AlwaysC    AlwaysKW Stmt
   | Assign     LHS Expr
   | Instance   Identifier [PortBinding] Identifier [PortBinding]
   | Function   (Maybe FuncRet) Identifier [(Bool, BlockItemDeclaration)] Stmt
@@ -90,6 +91,19 @@ data ModuleItem
   | Generate   [GenItem]
   deriving Eq
 
+data AlwaysKW
+  = Always
+  | AlwaysComb
+  | AlwaysFF
+  | AlwaysLatch
+  deriving Eq
+
+instance Show AlwaysKW where
+  show Always      = "always"
+  show AlwaysComb  = "always_comb"
+  show AlwaysFF    = "always_ff"
+  show AlwaysLatch = "always_latch"
+
 -- "function inputs and outputs are inferred to be of type reg if no internal
 -- data types for the ports are declared"
 
@@ -115,8 +129,7 @@ instance Show ModuleItem where
     MIIntegerV   nest -> show nest
     PortDecl   d r x -> printf "%s %s%s;" (show d) (showRange r) x
     LocalNet   t x v -> printf "%s%s%s;" (show t) x (showRangesOrAssignment v)
-    Always     Nothing  b -> printf "always\n%s" $ indent $ show b
+    AlwaysC    k b   -> printf "%s %s" (show k) (show b)
-    Always     (Just a) b -> printf "always @(%s)\n%s" (show a) $ indent $ show b
     Assign     a b   -> printf "assign %s = %s;" (show a) (show b)
     Instance   m params i ports
       | null params -> printf "%s %s %s;"     m                                  i (showPorts show ports)
@@ -290,6 +303,7 @@ data Stmt
   | NonBlockingAssignment LHS Expr
   | For                   (Identifier, Expr) Expr (Identifier, Expr) Stmt
   | If                    Expr Stmt Stmt
+  | Timing                Sense Stmt
   | Null
   deriving Eq
 
@@ -306,6 +320,7 @@ instance Show Stmt where
   show (For                   (a, b) c (d, e) f) = printf "for (%s = %s; %s; %s = %s)\n%s" a (show b) (show c) d (show e) $ indent $ show f
   show (If                    a b Null         ) = printf "if (%s)\n%s"           (show a) (indent $ show b)
   show (If                    a b c            ) = printf "if (%s)\n%s\nelse\n%s" (show a) (indent $ show b) (indent $ show c)
+  show (Timing                t s              ) = printf "@(%s) %s" (show t) (show s)
   show (Null                                   ) = ";"
 
 data BlockItemDeclaration

Language/SystemVerilog/Parser/Lex.x

@@ -58,6 +58,9 @@ $decimalDigit = [0-9]
 tokens :-
 
   "always"           { tok KW_always       }
+  "always_comb"      { tok KW_always_comb  }
+  "always_ff"        { tok KW_always_ff    }
+  "always_latch"     { tok KW_always_latch }
   "assign"           { tok KW_assign     }
   "begin"            { tok KW_begin      }
   "case"             { tok KW_case       }

Language/SystemVerilog/Parser/Parse.y

@@ -18,6 +18,9 @@ import Language.SystemVerilog.Parser.Tokens
 %token
 
 "always"           { Token KW_always       _ _ }
+"always_comb"      { Token KW_always_comb  _ _ }
+"always_ff"        { Token KW_always_ff    _ _ }
+"always_latch"     { Token KW_always_latch _ _ }
 "assign"           { Token KW_assign     _ _ }
 "begin"            { Token KW_begin      _ _ }
 "case"             { Token KW_case       _ _ }
@@ -228,12 +231,18 @@ ModuleItem :: { [ModuleItem] }
   | LocalparamDeclaration                                { map MILocalparam $1 }
   | IntegerDeclaration                                   { map MIIntegerV   $1 }
   | "assign" LHS "=" Expr ";"                            { [Assign $2 $4] }
-  | "always" opt(EventControl) Stmt                      { [Always $2 $3] }
+  | AlwaysKW Stmt                                        { [AlwaysC $1 $2] }
   | Identifier ParameterBindings ModuleInstantiations ";" { map (uncurry $ Instance $1 $2) $3 }
   | "function" opt(RangeOrType) Identifier FunctionItems Stmt "endfunction" { [Function $2 $3 $4 $5] }
   | "genvar" Identifiers ";"                             { map Genvar $2 }
   | "generate" GenItems "endgenerate"                    { [Generate $2] }
 
+AlwaysKW :: { AlwaysKW }
+  : "always"       { Always      }
+  | "always_comb"  { AlwaysComb  }
+  | "always_ff"    { AlwaysFF    }
+  | "always_latch" { AlwaysLatch }
+
 ModuleInstantiations :: { [(Identifier, [PortBinding])] }
   : ModuleInstantiation                          { [$1] }
   | ModuleInstantiations "," ModuleInstantiation { $1 ++ [$3] }
@@ -346,6 +355,7 @@ Stmt :: { Stmt }
   | LHS "=" Expr ";"                                 { BlockingAssignment $1 $3 }
   | LHS "<=" Expr ";"                                { NonBlockingAssignment $1 $3 }
   | "case" "(" Expr ")" Cases opt(CaseDefault) "endcase" { Case $3 $5 $6 }
+  | EventControl Stmt                                { Timing $1 $2 }
 
 BlockItemDeclarations :: { [BlockItemDeclaration] }
   : BlockItemDeclaration                       { $1 }