additional codegen test coverage

- assertions, gen case, and inout
- simplify block codegen
- remove blank lines in tasks with no inputs

test/basic/assert.sv

@@ -0,0 +1,12 @@
+module Module(input clock, input clear, input data);
+    logic x, y;
+    assign y = data;
+    assign x = y;
+    assert property (
+        @(posedge clock) disable iff(clear) x == y
+    );
+    task hello;
+        $display("Hello!");
+        assert property (x == y);
+    endtask
+endmodule