additional interface conversion test coverage

This commit is contained in:
Zachary Snow
2020-12-11 12:41:20 -07:00
parent c5b066d5eb
commit 2311d3e2d6
17 changed files with 169 additions and 17 deletions
+23
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@@ -0,0 +1,23 @@
interface Interface;
integer x;
endinterface
module Single(intf);
Interface intf;
initial #1 $display("Single %0d", intf.x);
endmodule
module Group(intfs);
parameter WIDTH = 1;
Interface intfs [WIDTH];
initial $display("Group %0d", WIDTH);
for (genvar i = 0; i < WIDTH; ++i)
Single s(intfs[i]);
endmodule
module top;
Interface intfs[8]();
for (genvar i = 0; i < 8; ++i)
initial intfs[i].x = i ** 3;
Group #(.WIDTH(8)) g(intfs);
endmodule
+8
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@@ -0,0 +1,8 @@
module top;
initial $display("Group %0d", 8);
generate
genvar i;
for (i = 0; i < 8; i = i + 1)
initial #1 $display("Single %0d", i ** 3);
endgenerate
endmodule
+9
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@@ -0,0 +1,9 @@
interface Interface(output out);
assign out = 1;
endinterface
module top;
logic x;
Interface intfs[1](x);
initial $display(x);
endmodule
+4
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@@ -0,0 +1,4 @@
module top;
wire x = 1;
initial $display(x);
endmodule
+7
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@@ -33,6 +33,13 @@ module ModuleN(intf);
Interface intf;
`SHADOW
initial #1 $display("ModuleN got %0d", intf.x);
typedef struct packed {
logic a, b;
} Struct;
Struct [1:0] structs;
assign structs[1].a = structs[0].b;
assign structs[0].a = structs[1].b;
endmodule
module top;
+10
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@@ -0,0 +1,10 @@
interface Interface;
parameter type T = logic [2:0];
initial $display($bits(T));
endinterface
module top;
Interface #(logic) a();
Interface #(byte) b();
Interface c();
endmodule
+5
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@@ -0,0 +1,5 @@
module top;
initial $display(1);
initial $display(8);
initial $display(3);
endmodule
+15
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@@ -0,0 +1,15 @@
interface Interface(input x);
initial $display("Hello!");
endinterface
module Module(i);
Interface i;
initial #1 $display(i.x);
endmodule
module top;
Interface i1();
Module m1(i1);
Interface i2(.x());
Module m2(i2);
endmodule
+15
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@@ -0,0 +1,15 @@
module Module(x);
input wire x;
initial $display("Hello!");
initial #1 $display(x);
endmodule
module top;
generate
if (1) begin
wire x;
Module m1(x);
Module m2(x);
end
endgenerate
endmodule