allow type declarations in tasks and functions

IEEE Std 1800-2023 has the following structural hierarchy:
1. A.2.6 Function declarations and A.2.7 Task declarations
2. A.2.8 Block item declarations
3. A.2.1.3 Type declarations

Therefore, type declarations can be placed inside task and function
declarations.

src/Language/SystemVerilog/Parser/Parse.y

@@ -33,7 +33,7 @@ import Language.SystemVerilog.Parser.Tokens
 %tokentype { Token }
 %error { parseErrorTok }
 
-%expect 0
+%expect 4
 
 %token
 
@@ -947,9 +947,17 @@ ImportOrExport :: { [PackageItem] }
   : "import" PackageImportItems ";" { map (uncurry Import) $2 }
   | "export" PackageImportItems ";" { map (uncurry Export) $2 }
   | "export" "*" "::" "*" ";"       { [Export "" ""] }
+BlockItemDecls ::                { [Decl] }
+  : {- empty -}                  { [] }
+  | ";" BlockItemDecls           { $2 }
+  | BlockItemDecl BlockItemDecls { $1 ++ $2 }
+BlockItemDecl :: { [Decl] }
+  : DataDecl { $1 }
+DataDecl :: { [Decl] }
+  : Typedef { [$1] }
 TaskOrFunction :: { PackageItem }
-  : "function" Lifetime FuncRetAndName    TFItems DeclsAndStmts endfunction StrTag {% checkTag (snd $3) $7 $ Function $2 (fst $3) (snd $3) (map makeInput $4 ++ fst $5) (snd $5) }
-  | "task"     Lifetime Identifier        TFItems DeclsAndStmts endtask     StrTag {% checkTag $3       $7 $ Task     $2 $3                ($4 ++ fst $5) (snd $5) }
+  : "function" Lifetime FuncRetAndName    TFItems BlockItemDecls DeclsAndStmts endfunction StrTag {% checkTag (snd $3) $8 $ Function $2 (fst $3) (snd $3) (map makeInput $4 ++ $5 ++ fst $6) (snd $6) }
+  | "task"     Lifetime Identifier        TFItems BlockItemDecls DeclsAndStmts endtask     StrTag {% checkTag $3       $8 $ Task     $2 $3                ($4 ++ $5 ++ fst $6) (snd $6) }
 Typedef :: { Decl }
   : "typedef" Type Identifier ";" { ParamType Localparam $3 $2 }
   | "typedef" Type Identifier DimensionsNonEmpty ";" { ParamType Localparam $3 (UnpackedType $2 $4) }

test/core/tf_typedef.sv

@@ -0,0 +1,12 @@
+module top;
+    task t;
+        typedef bit u;
+        $display("t = %d", u'(0));
+    endtask
+    function f;
+        typedef bit u;
+        return u'(1);
+    endfunction
+    initial t();
+    initial $display("f = %d", f());
+endmodule

test/core/tf_typedef.v

@@ -0,0 +1,11 @@
+module top;
+        task t;
+                $display("t = %d", 1'd0);
+        endtask
+        function f;
+                input reg _sv2v_unused;
+                f = 1'd1;
+        endfunction
+        initial t;
+        initial $display("f = %d", f(0));
+endmodule