fix double backtick handling in backtick string

src/Language/SystemVerilog/Parser/Preprocess.hs

@@ -630,6 +630,10 @@ handleBacktickString = do
                     if null macroStack
                         then lexicalError "`\\`\" is not allowed outside of macros"
                         else loop
+                '`' : '`' : _ -> do
+                    '`' <- takeChar
+                    '`' <- takeChar
+                    loop
                 '`' : _ -> do
                     handleDirective True
                     loop

test/lex/macro_string.sv

@@ -0,0 +1,15 @@
+`define PRINT(str, num) $display(`"StrIs``str NumIs``num`");
+
+module top;
+    initial begin
+
+        `PRINT(FOO, 0)
+        `PRINT(BAR, 1)
+        `PRINT(BAZ, 2)
+
+        `PRINT(A, 1)
+        `PRINT(B, 2)
+        `PRINT(C, 3)
+
+    end
+endmodule

test/lex/macro_string.v

@@ -0,0 +1 @@
+`include "macro_string.sv"