mirror of https://github.com/zachjs/sv2v.git
add generated number tests
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@ -38,6 +38,7 @@ All of sv2v's dependencies are free and open-source.
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* Test Dependencies
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* Test Dependencies
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* [Icarus Verilog](http://iverilog.icarus.com) - for Verilog simulation
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* [Icarus Verilog](http://iverilog.icarus.com) - for Verilog simulation
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* [shUnit2](https://github.com/kward/shunit2) - test framework
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* [shUnit2](https://github.com/kward/shunit2) - test framework
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* Python (any version) - for generating certain test cases
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## Installation
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## Installation
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@ -0,0 +1 @@
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*.sv
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@ -0,0 +1,50 @@
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import math
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import sys
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def gen_digits(digits, size):
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if size <= 0:
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raise Exception("size must be positive")
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elif size == 1:
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for digit in digits:
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yield digit
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else:
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for base in gen_digits(digits, size - 1):
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for digit in digits:
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yield base + digit
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def gen(max_length, code, base, digits):
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for length in range(1, max_length + 1):
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min_bits = math.floor(1 + (length - 1) * math.log(base, 2))
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max_bits = math.ceil(length * math.log(base, 2))
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for number in gen_digits(digits, length):
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yield "'" + code + number
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yield "'s" + code + number
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number_bin = number.replace("x", "0").replace("z", "0")
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min_value = max(1, int(number_bin, base)) + 1
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curr_min_bits = max(min_bits, math.ceil(math.log(min_value, 2)))
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for bits in range(int(curr_min_bits), int(max_bits + 1)):
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size = str(bits)
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yield size + "'" + code + number
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yield size + "'s" + code + number
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if __name__ == "__main__":
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assert len(sys.argv) == 5
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max_length = int(sys.argv[1])
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code = sys.argv[2]
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base = int(sys.argv[3])
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digits = sys.argv[4]
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print('`define T(n) $display(`"n => %b => %0d`", n, $bits(n));')
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print("module top;")
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print("initial begin")
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for number in gen(max_length, code, base, digits):
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print("`T({})".format(number))
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print("end")
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print("endmodule")
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@ -0,0 +1,6 @@
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#!/bin/bash
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python gen.py 4 b 2 01xz > binary.sv
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python gen.py 2 o 8 01234567xz > octal.sv
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python gen.py 2 d 10 0123456789 > decimal.sv
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python gen.py 2 h 16 0123456789abcdefxz > hex.sv
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source ../lib/runner.sh
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