fix bare input signed declarations for inlined modules

CHANGELOG.md

@@ -11,6 +11,8 @@
 * Fixed `--write path/to/dir/` with directives like `` `default_nettype ``
 * Fixed `logic` incorrectly converted to `wire` even when provided to a task or
   function output port
+* Fixed `input signed` ports of interface-using modules producing invalid
+  declarations after inlining
 * Fixed `` `resetall `` not resetting the `` `default_nettype ``
 
 ### Other Enhancements

src/Convert/Interface.hs

@@ -633,8 +633,7 @@ inlineInstance global ranges modportBindings items partName
         removeDeclDir (Variable _ t x a e) =
             Variable Local t' x a e
             where t' = case t of
-                    Implicit Unspecified rs ->
+                    Implicit sg rs -> IntegerVector TLogic sg rs
-                        IntegerVector TLogic Unspecified rs
                     _ -> t
         removeDeclDir decl@Net{} =
             traverseNetAsVar removeDeclDir decl

test/core/interface_input_type.sv

@@ -0,0 +1,14 @@
+module top;
+    intf i();
+    mod m(i, 1'b1);
+    initial #1 $display("%b", i.y);
+endmodule
+module mod(
+    input intf i,
+    input signed x
+);
+    initial i.y = x;
+endmodule
+interface intf;
+    logic [1:0] y;
+endinterface

test/core/interface_input_type.v

@@ -0,0 +1,3 @@
+module top;
+    initial #1 $display("%b", 2'b11);
+endmodule