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allow for stray semicolons in module items; allow for multiple struct field declarations on one line

This commit is contained in:
Zachary Snow 2019-03-29 16:48:58 -04:00
parent 5dc049b9e5
commit 1a170f41c2
1 changed files with 5 additions and 4 deletions
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9
src/Language/SystemVerilog/Parser/Parse.y
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@ -287,10 +287,10 @@ EnumItems :: { [(Identifier, Maybe Expr)] }
: VariablePortIdentifiers { $1 }
StructItems :: { [(Type, Identifier)] }
: StructItem { [$1] }
| StructItems StructItem { $1 ++ [$2] }
StructItem :: { (Type, Identifier) }
: Type Identifier ";" { ($1, $2) }
: StructItem { $1 }
| StructItems StructItem { $1 ++ $2 }
StructItem :: { [(Type, Identifier)] }
: Type Identifiers ";" { map (\a -> ($1, a)) $2 }
Packing :: { Packing }
: "packed" Signing { Packed $2 }
@ -395,6 +395,7 @@ Direction :: { Direction }
ModuleItems :: { [ModuleItem] }
: {- empty -} { [] }
| ModuleItems ModuleItem { $1 ++ $2 }
| ModuleItems ";" { $1 }
ModuleItem :: { [ModuleItem] }
-- This item covers module instantiations and all declarations