allow typename resolution of non-vector types

src/Convert/Typedef.hs

@@ -94,5 +94,5 @@ resolveType types (Alias Nothing st rs1) =
         (Union           p l rs2) -> Union           p l $ rs1 ++ rs2
         (InterfaceT     x my rs2) -> InterfaceT     x my $ rs1 ++ rs2
         (Alias          ps x rs2) -> Alias          ps x $ rs1 ++ rs2
-        (IntegerAtom   kw _ ) -> error $ "resolveType encountered packed `" ++ (show kw) ++ "` on " ++ st
-        (NonInteger    kw   ) -> error $ "resolveType encountered packed `" ++ (show kw) ++ "` on " ++ st
+        (IntegerAtom   kw sg    ) -> nullRange (IntegerAtom kw sg) rs1
+        (NonInteger    kw       ) -> nullRange (NonInteger  kw   ) rs1

src/Language/SystemVerilog/AST/Type.hs

@@ -17,6 +17,7 @@ module Language.SystemVerilog.AST.Type
     , IntegerAtomType   (..)
     , NonIntegerType    (..)
     , typeRanges
+    , nullRange
     ) where
 
 import Text.Printf (printf)

test/basic/enum.sv

@@ -31,6 +31,10 @@ typedef enum Foo_t {
     H_1 = 'b1, H_2 = 'b0
 } EnumH;
 
+typedef enum int {
+    I_1, I_2
+} EnumI;
+
 `define PRINT(name, val) \
     dummy``name = name``_``val; \
     $display("%h %h %0d %0d", \
@@ -50,6 +54,7 @@ module top;
     EnumF dummyF;
     EnumG dummyG;
     EnumH dummyH;
+    EnumI dummyI;
 
     initial begin
 
@@ -85,5 +90,8 @@ module top;
         `PRINT_UNSIZED(H, 1)
         `PRINT_UNSIZED(H, 2)
 
+        `PRINT_UNSIZED(I, 1)
+        `PRINT_UNSIZED(I, 2)
+
     end
 endmodule

test/basic/enum.v

@@ -18,6 +18,7 @@ module top;
     reg [0:0] dummyF;
     reg [0:0] dummyG;
     reg [3:0] dummyH;
+    reg [31:0] dummyI;
 
     initial begin
 
@@ -53,6 +54,9 @@ module top;
         `PRINT_UNSIZED(H, 'b1)
         `PRINT_UNSIZED(H, 'b0)
 
+        `PRINT_UNSIZED(I, 'b0)
+        `PRINT_UNSIZED(I, 'b1)
+
     end
 endmodule