language support for streaming operators

src/Convert/Struct.hs

@@ -386,6 +386,11 @@ convertAsgn structs types (lhs, expr) =
                     (tf, rs) -> tf $ tail rs
         convertSubExpr (Concat exprs) =
             (Implicit Unspecified [], Concat $ map (snd . convertSubExpr) exprs)
+        convertSubExpr (Stream o e exprs) =
+            (Implicit Unspecified [], Stream o e' exprs')
+            where
+                e' = (snd . convertSubExpr) e
+                exprs' = map (snd . convertSubExpr) exprs
         convertSubExpr (BinOp op e1 e2) =
             (Implicit Unspecified [], BinOp op e1' e2')
             where

src/Convert/Traverse.hs

@@ -429,6 +429,10 @@ traverseNestedExprsM mapper = exprMapper
             return $ Repeat e' l'
         em (Concat     l) =
             mapM exprMapper l >>= return . Concat
+        em (Stream o e l) = do
+            e' <- exprMapper e
+            l' <- mapM exprMapper l
+            return $ Stream o e' l'
         em (Call    ps f (Args l p)) = do
             l' <- mapM maybeExprMapper l
             pes <- mapM maybeExprMapper $ map snd p

src/Language/SystemVerilog/AST/Expr.hs

@@ -39,6 +39,7 @@ data Expr
     | Bit     Expr Expr
     | Repeat  Expr [Expr]
     | Concat  [Expr]
+    | Stream  StreamOp Expr [Expr]
     | Call    (Maybe Identifier) Identifier Args
     | UniOp   UniOp Expr
     | BinOp   BinOp Expr Expr
@@ -58,6 +59,7 @@ instance Show Expr where
     show (Range   e m r) = printf "%s[%s%s%s]" (show e) (show $ fst r) (show m) (show $ snd r)
     show (Repeat  e l  ) = printf "{%s {%s}}"  (show e) (commas $ map show l)
     show (Concat  l    ) = printf "{%s}"                (commas $ map show l)
+    show (Stream  o e l) = printf "{%s %s%s}"  (show o) (show e) (show $ Concat l)
     show (UniOp   a b  ) = printf "(%s %s)"    (show a) (show b)
     show (BinOp   o a b) = printf "(%s %s %s)" (show a) (show o) (show b)
     show (Dot     e n  ) = printf "%s.%s"      (show e) n

src/Language/SystemVerilog/AST/Op.hs

@@ -2,13 +2,14 @@
  - Author: Zachary Snow <zach@zachjs.com>
  - Initial Verilog AST Author: Tom Hawkins <tomahawkins@gmail.com>
  -
- - SystemVerilog operators (unary, binary, and assignment)
+ - SystemVerilog operators (unary, binary, assignment, and stream)
  -}
 
 module Language.SystemVerilog.AST.Op
-    ( UniOp  (..)
-    , BinOp  (..)
-    , AsgnOp (..)
+    ( UniOp    (..)
+    , BinOp    (..)
+    , AsgnOp   (..)
+    , StreamOp (..)
     ) where
 
 data UniOp
@@ -101,3 +102,12 @@ data AsgnOp
 instance Show AsgnOp where
     show AsgnOpEq = "="
     show (AsgnOp op) = (show op) ++ "="
+
+data StreamOp
+    = StreamL
+    | StreamR
+    deriving (Eq, Ord)
+
+instance Show StreamOp where
+    show StreamL  = "<<"
+    show StreamR  = ">>"

src/Language/SystemVerilog/Parser/Parse.y

@@ -834,8 +834,8 @@ Expr :: { Expr }
   | Identifier "::" Identifier  { PSIdent $1 $3 }
   | Expr PartSelect             { Range $1 (fst $2) (snd $2) }
   | Expr "[" Expr "]"           { Bit   $1 $3 }
-  | "{" Expr "{" Exprs "}" "}"  { Repeat $2 $4 }
-  | "{" Exprs "}"               { Concat $2 }
+  | "{" Expr Concat "}"         { Repeat $2 $3 }
+  | Concat                      { Concat $1 }
   | Expr "?" Expr ":" Expr      { Mux $1 $3 $5 }
   | CastingType "'" "(" Expr ")" { Cast (Left            $1) $4 }
   | Number      "'" "(" Expr ")" { Cast (Right $ Number  $1) $4 }
@@ -843,6 +843,8 @@ Expr :: { Expr }
   | Identifier "::" Identifier  "'" "(" Expr ")" { Cast (Left $ Alias (Just $1) $3 []) $6 }
   | Expr "." Identifier         { Dot $1 $3 }
   | "'" "{" PatternItems "}"    { Pattern $3 }
+  | "{" StreamOp StreamSize Concat "}" { Stream $2 $3           $4 }
+  | "{" StreamOp            Concat "}" { Stream $2 (Number "1") $3 }
   -- binary expressions
   | Expr "||"  Expr { BinOp LogOr  $1 $3 }
   | Expr "&&"  Expr { BinOp LogAnd $1 $3 }
@@ -896,6 +898,16 @@ PatternNamedItem :: { (Identifier, Expr) }
 PatternUnnamedItems :: { [Expr] }
   : Exprs { $1 }
 
+Concat :: { [Expr] }
+  : "{" Exprs "}" { $2 }
+
+StreamOp :: { StreamOp }
+  : "<<" { StreamL }
+  | ">>" { StreamR }
+StreamSize :: { Expr }
+  : TypeNonIdent { Bits $ Left $1 }
+  | Expr         { $1 }
+
 GenItemOrNull :: { GenItem }
   : GenItem { $1 }
   | ";"     { GenNull }