fixed off by 1 in logic conversion

2019-04-23 00:33:41 -04:00 · 2019-04-23 00:33:41 -04:00 · 04983b0cd5
parent 7734fa539d
commit 04983b0cd5
1 changed files with 1 additions and 1 deletions
--- a/src/Convert/Logic.hs
+++ b/src/Convert/Logic.hs
@ -97,7 +97,7 @@ convertDescription ports orig =
                            collectNestedExprsM exprIdents expr
                        tmp = "sv2v_tmp_" ++ instanceName ++ "_" ++ portName
                        tmpExpr = Ident tmp
-                        t = Net TWire [(Bits $ Right expr, Number "0")]
+                        t = Net TWire [(Bits $ Right expr, Number "1")]
                        items =
                            [ MIDecl $ Variable Local t tmp [] Nothing
                            , AlwaysC AlwaysComb $ AsgnBlk AsgnOpEq lhs tmpExpr]