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fixed off by 1 in logic conversion

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Zachary Snow
2019-04-23 00:33:41 -04:00
parent 7734fa539d
commit 04983b0cd5
1 changed files with 1 additions and 1 deletions
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src/Convert/Logic.hs
+1 -1
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@@ -97,7 +97,7 @@ convertDescription ports orig =
collectNestedExprsM exprIdents expr
tmp = "sv2v_tmp_" ++ instanceName ++ "_" ++ portName
tmpExpr = Ident tmp
t = Net TWire [(Bits $ Right expr, Number "0")]
t = Net TWire [(Bits $ Right expr, Number "1")]
items =
[ MIDecl $ Variable Local t tmp [] Nothing
, AlwaysC AlwaysComb $ AsgnBlk AsgnOpEq lhs tmpExpr]